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Diffstat (limited to 'src/gpgpu-sim/gpu-sim.cc')
-rw-r--r--src/gpgpu-sim/gpu-sim.cc46
1 files changed, 46 insertions, 0 deletions
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index d085805..006d243 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -87,6 +87,14 @@ unsigned long long gpu_tot_sim_cycle = 0;
// performance counter for stalls due to congestion.
unsigned int gpu_stall_dramfull = 0;
unsigned int gpu_stall_icnt2sh = 0;
+unsigned long long partiton_reqs_in_parallel = 0;
+unsigned long long partiton_reqs_in_parallel_total = 0;
+unsigned long long partiton_reqs_in_parallel_util = 0;
+unsigned long long partiton_reqs_in_parallel_util_total = 0;
+unsigned long long gpu_sim_cycle_parition_util = 0;
+unsigned long long gpu_tot_sim_cycle_parition_util = 0;
+unsigned long long partiton_replys_in_parallel = 0;
+unsigned long long partiton_replys_in_parallel_total = 0;
/* Clock Domains */
@@ -786,6 +794,10 @@ void gpgpu_sim::init()
gpu_sim_insn = 0;
last_gpu_sim_insn = 0;
m_total_cta_launched=0;
+ partiton_reqs_in_parallel = 0;
+ partiton_replys_in_parallel = 0;
+ partiton_reqs_in_parallel_util = 0;
+ gpu_sim_cycle_parition_util = 0;
reinit_clock_domains();
set_param_gpgpu_num_shaders(m_config.num_shader());
@@ -822,8 +834,17 @@ void gpgpu_sim::update_stats() {
gpu_tot_sim_cycle += gpu_sim_cycle;
gpu_tot_sim_insn += gpu_sim_insn;
gpu_tot_issued_cta += m_total_cta_launched;
+ partiton_reqs_in_parallel_total += partiton_reqs_in_parallel;
+ partiton_replys_in_parallel_total += partiton_replys_in_parallel;
+ partiton_reqs_in_parallel_util_total += partiton_reqs_in_parallel_util;
+ gpu_tot_sim_cycle_parition_util += gpu_sim_cycle_parition_util ;
gpu_sim_cycle = 0;
+ partiton_reqs_in_parallel = 0;
+ partiton_replys_in_parallel = 0;
+ partiton_reqs_in_parallel_util = 0;
+ gpu_sim_cycle_parition_util = 0;
+ gpu_tot_sim_cycle = 0;
gpu_sim_insn = 0;
m_total_cta_launched = 0;
}
@@ -1007,6 +1028,21 @@ void gpgpu_sim::gpu_print_stat()
printf("gpu_stall_dramfull = %d\n", gpu_stall_dramfull);
printf("gpu_stall_icnt2sh = %d\n", gpu_stall_icnt2sh );
+ printf("partiton_reqs_in_parallel = %lld\n", partiton_reqs_in_parallel);
+ printf("partiton_reqs_in_parallel_total = %lld\n", partiton_reqs_in_parallel_total );
+ printf("partiton_level_parallism = %12.4f\n", (float)partiton_reqs_in_parallel / gpu_sim_cycle);
+ printf("partiton_level_parallism_total = %12.4f\n", (float)(partiton_reqs_in_parallel+partiton_reqs_in_parallel_total) / (gpu_tot_sim_cycle+gpu_sim_cycle) );
+ printf("partiton_reqs_in_parallel_util = %lld\n", partiton_reqs_in_parallel_util);
+ printf("partiton_reqs_in_parallel_util_total = %lld\n", partiton_reqs_in_parallel_util_total );
+ printf("gpu_sim_cycle_parition_util = %lld\n", gpu_sim_cycle_parition_util);
+ printf("gpu_tot_sim_cycle_parition_util = %lld\n", gpu_tot_sim_cycle_parition_util );
+ printf("partiton_level_parallism_util = %12.4f\n", (float)partiton_reqs_in_parallel_util / gpu_sim_cycle_parition_util);
+ printf("partiton_level_parallism_util_total = %12.4f\n", (float)(partiton_reqs_in_parallel_util+partiton_reqs_in_parallel_util_total) / (gpu_sim_cycle_parition_util+gpu_tot_sim_cycle_parition_util) );
+ printf("partiton_replys_in_parallel = %lld\n", partiton_replys_in_parallel);
+ printf("partiton_replys_in_parallel_total = %lld\n", partiton_replys_in_parallel_total );
+ printf("L2_BW = %12.4f GB/Sec\n", ((float)(partiton_replys_in_parallel * 32) / (gpu_sim_cycle * m_config.icnt_period)) / 1000000000);
+ printf("L2_BW_total = %12.4f GB/Sec\n", ((float)((partiton_replys_in_parallel+partiton_replys_in_parallel_total) * 32) / ((gpu_tot_sim_cycle+gpu_sim_cycle) * m_config.icnt_period)) / 1000000000 );
+
time_t curr_time;
time(&curr_time);
unsigned long long elapsed_time = MAX( curr_time - g_simulation_starttime, 1 );
@@ -1412,6 +1448,7 @@ void gpgpu_sim::cycle()
for (unsigned i=0;i<m_shader_config->n_simt_clusters;i++)
m_cluster[i]->icnt_cycle();
}
+ unsigned partiton_replys_in_parallel_per_cycle = 0;
if (clock_mask & ICNT) {
// pop from memory controller to interconnect
for (unsigned i=0;i<m_memory_config->m_n_mem_sub_partition;i++) {
@@ -1424,6 +1461,7 @@ void gpgpu_sim::cycle()
mf->set_status(IN_ICNT_TO_SHADER,gpu_sim_cycle+gpu_tot_sim_cycle);
::icnt_push( m_shader_config->mem2device(i), mf->get_tpc(), mf, response_size );
m_memory_sub_partition[i]->pop();
+ partiton_replys_in_parallel_per_cycle++;
} else {
gpu_stall_icnt2sh++;
}
@@ -1432,6 +1470,7 @@ void gpgpu_sim::cycle()
}
}
}
+ partiton_replys_in_parallel += partiton_replys_in_parallel_per_cycle;
if (clock_mask & DRAM) {
for (unsigned i=0;i<m_memory_config->m_n_mem;i++){
@@ -1444,6 +1483,7 @@ void gpgpu_sim::cycle()
}
// L2 operations follow L2 clock domain
+ unsigned partiton_reqs_in_parallel_per_cycle = 0;
if (clock_mask & L2) {
m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].clear();
for (unsigned i=0;i<m_memory_config->m_n_mem_sub_partition;i++) {
@@ -1455,11 +1495,17 @@ void gpgpu_sim::cycle()
} else {
mem_fetch* mf = (mem_fetch*) icnt_pop( m_shader_config->mem2device(i) );
m_memory_sub_partition[i]->push( mf, gpu_sim_cycle + gpu_tot_sim_cycle );
+ partiton_reqs_in_parallel_per_cycle++;
}
m_memory_sub_partition[i]->cache_cycle(gpu_sim_cycle+gpu_tot_sim_cycle);
m_memory_sub_partition[i]->accumulate_L2cache_stats(m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX]);
}
}
+ partiton_reqs_in_parallel += partiton_reqs_in_parallel_per_cycle;
+ if(partiton_reqs_in_parallel_per_cycle > 0){
+ partiton_reqs_in_parallel_util += partiton_reqs_in_parallel_per_cycle;
+ gpu_sim_cycle_parition_util++;
+ }
if (clock_mask & ICNT) {
icnt_transfer();