diff options
Diffstat (limited to 'src/gpgpu-sim/gpu-sim.cc')
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.cc | 194 |
1 files changed, 107 insertions, 87 deletions
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 34bc7d9..5d75e50 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -60,12 +60,12 @@ #include "../debug.h" #include "../gpgpusim_entrypoint.h" #include "../statwrapper.h" +#include "../trace-driven/trace_driven.h" #include "../trace.h" #include "mem_latency_stat.h" #include "power_stat.h" #include "stats.h" #include "visualizer.h" -#include "../trace-driven/trace_driven.h" #ifdef GPGPUSIM_POWER_MODEL #include "power_interface.h" @@ -130,9 +130,11 @@ void power_config::reg_options(class OptionParser *opp) { } void memory_config::reg_options(class OptionParser *opp) { - option_parser_register(opp, "-gpgpu_perf_sim_memcpy", OPT_BOOL, &m_perf_sim_memcpy, - "Fill the L2 cache on memcpy", "1"); - option_parser_register(opp, "-gpgpu_simple_dram_model", OPT_BOOL, &simple_dram_model, + option_parser_register(opp, "-gpgpu_perf_sim_memcpy", OPT_BOOL, + &m_perf_sim_memcpy, "Fill the L2 cache on memcpy", + "1"); + option_parser_register(opp, "-gpgpu_simple_dram_model", OPT_BOOL, + &simple_dram_model, "simple_dram_model with fixed latency and BW", "0"); option_parser_register(opp, "-gpgpu_dram_scheduler", OPT_INT32, &scheduler_type, "0 = fifo, 1 = FR-FCFS (defaul)", @@ -187,11 +189,12 @@ void memory_config::reg_options(class OptionParser *opp) { "DRAM timing parameters = " "{nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}", "4:2:8:12:21:13:34:9:4:5:13:1:0:0"); - option_parser_register(opp, "-gpgpu_l2_rop_latency", OPT_UINT32, &rop_latency, + option_parser_register(opp, "-gpgpu_l2_rop_latency", OPT_UINT32, &rop_latency, "ROP queue latency (default 85)", "85"); option_parser_register(opp, "-dram_latency", OPT_UINT32, &dram_latency, "DRAM latency (default 30)", "30"); - option_parser_register(opp, "-dram_dual_bus_interface", OPT_UINT32, &dual_bus_interface, + option_parser_register(opp, "-dram_dual_bus_interface", OPT_UINT32, + &dual_bus_interface, "dual_bus_interface (default = 0) ", "0"); option_parser_register(opp, "-dram_bnk_indexing_policy", OPT_UINT32, &dram_bnk_indexing_policy, @@ -203,11 +206,13 @@ void memory_config::reg_options(class OptionParser *opp) { "dram_bnkgrp_indexing_policy (0 = take higher bits, 1 " "= take lower bits) (Default = 0)", "0"); - option_parser_register(opp, "-dram_seperate_write_queue_enable", OPT_BOOL, &seperate_write_queue_enabled, + option_parser_register(opp, "-dram_seperate_write_queue_enable", OPT_BOOL, + &seperate_write_queue_enabled, "Seperate_Write_Queue_Enable", "0"); - option_parser_register(opp, "-dram_write_queue_size", OPT_CSTR, &write_queue_size_opt, - "Write_Queue_Size", "32:28:16"); - option_parser_register(opp, "-dram_elimnate_rw_turnaround", OPT_BOOL, &elimnate_rw_turnaround, + option_parser_register(opp, "-dram_write_queue_size", OPT_CSTR, + &write_queue_size_opt, "Write_Queue_Size", "32:28:16"); + option_parser_register( + opp, "-dram_elimnate_rw_turnaround", OPT_BOOL, &elimnate_rw_turnaround, "elimnate_rw_turnaround i.e set tWTR and tRTW = 0", "0"); option_parser_register(opp, "-icnt_flit_size", OPT_UINT32, &icnt_flit_size, "icnt_flit_size", "32"); @@ -245,11 +250,12 @@ void shader_core_config::reg_options(class OptionParser *opp) { " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_" "alloc>,<mshr>:<N>:<merge>,<mq> | none}", "none"); - option_parser_register(opp, "-gpgpu_l1_banks", OPT_UINT32, &m_L1D_config.l1_banks, - "The number of L1 cache banks", "1"); - option_parser_register(opp, "-gpgpu_l1_latency", OPT_UINT32, &m_L1D_config.l1_latency, - "L1 Hit Latency", "1"); - option_parser_register(opp, "-gpgpu_smem_latency", OPT_UINT32, &smem_latency, + option_parser_register(opp, "-gpgpu_l1_banks", OPT_UINT32, + &m_L1D_config.l1_banks, "The number of L1 cache banks", + "1"); + option_parser_register(opp, "-gpgpu_l1_latency", OPT_UINT32, + &m_L1D_config.l1_latency, "L1 Hit Latency", "1"); + option_parser_register(opp, "-gpgpu_smem_latency", OPT_UINT32, &smem_latency, "smem Latency", "3"); option_parser_register(opp, "-gpgpu_cache:dl1PrefL1", OPT_CSTR, &m_L1D_config.m_config_stringPrefL1, @@ -263,7 +269,7 @@ void shader_core_config::reg_options(class OptionParser *opp) { " {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_" "alloc>,<mshr>:<N>:<merge>,<mq> | none}", "none"); - option_parser_register(opp, "-gpgpu_gmem_skip_L1D", OPT_BOOL, &gmem_skip_L1D, + option_parser_register(opp, "-gpgpu_gmem_skip_L1D", OPT_BOOL, &gmem_skip_L1D, "global memory access skip L1D cache (implements " "-Xptxas -dlcm=cg, default=no skip)", "0"); @@ -315,8 +321,8 @@ void shader_core_config::reg_options(class OptionParser *opp) { option_parser_register( opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size, "Size of shared memory per shader core (default 16kB)", "16384"); - option_parser_register(opp, "-gpgpu_adaptive_cache_config", OPT_UINT32, &adaptive_cache_config, - "adaptive_cache_config", "0"); + option_parser_register(opp, "-gpgpu_adaptive_cache_config", OPT_UINT32, + &adaptive_cache_config, "adaptive_cache_config", "0"); option_parser_register( opp, "-gpgpu_shmem_sizeDefault", OPT_UINT32, &gpgpu_shmem_sizeDefault, "Size of shared memory per shader core (default 16kB)", "16384"); @@ -339,7 +345,8 @@ void shader_core_config::reg_options(class OptionParser *opp) { "Number of portions a warp is divided into for shared " "memory bank conflict check ", "2"); - option_parser_register(opp, "-gpgpu_mem_unit_ports", OPT_INT32, &mem_unit_ports, + option_parser_register( + opp, "-gpgpu_mem_unit_ports", OPT_INT32, &mem_unit_ports, "The number of memory transactions allowed per core cycle", "1"); option_parser_register(opp, "-gpgpu_shmem_warp_parts", OPT_INT32, &mem_warp_parts, @@ -365,10 +372,11 @@ void shader_core_config::reg_options(class OptionParser *opp) { option_parser_register( opp, "-gpgpu_reg_bank_use_warp_id", OPT_BOOL, &gpgpu_reg_bank_use_warp_id, "Use warp ID in mapping registers to banks (default = off)", "0"); - option_parser_register(opp, "-gpgpu_sub_core_model", OPT_BOOL, &sub_core_model, + option_parser_register(opp, "-gpgpu_sub_core_model", OPT_BOOL, + &sub_core_model, "Sub Core Volta/Pascal model (default = off)", "0"); - option_parser_register(opp, "-gpgpu_enable_specialized_operand_collector", OPT_BOOL, - &enable_specialized_operand_collector, + option_parser_register(opp, "-gpgpu_enable_specialized_operand_collector", + OPT_BOOL, &enable_specialized_operand_collector, "enable_specialized_operand_collector", "1"); option_parser_register(opp, "-gpgpu_operand_collector_num_units_sp", OPT_INT32, &gpgpu_operand_collector_num_units_sp, @@ -492,9 +500,9 @@ void shader_core_config::reg_options(class OptionParser *opp) { "1"); option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_INT32, &gpgpu_num_tensor_core_units, - "Number of tensor_core units (default=1)", - "0"); - option_parser_register(opp, "-gpgpu_num_mem_units", OPT_INT32, &gpgpu_num_mem_units, + "Number of tensor_core units (default=1)", "0"); + option_parser_register( + opp, "-gpgpu_num_mem_units", OPT_INT32, &gpgpu_num_mem_units, "Number if ldst units (default=1) WARNING: not hooked up to anything", "1"); option_parser_register( @@ -511,31 +519,43 @@ void shader_core_config::reg_options(class OptionParser *opp) { option_parser_register( opp, "-gpgpu_concurrent_kernel_sm", OPT_BOOL, &gpgpu_concurrent_kernel_sm, "Support concurrent kernels on a SM (default = disabled)", "0"); - option_parser_register(opp, "-gpgpu_perfect_inst_const_cache", OPT_BOOL, &perfect_inst_const_cache, - "perfect inst and const cache mode, so all inst and const hits in the cache(default = disabled)", - "0"); - option_parser_register(opp, "-gpgpu_inst_fetch_throughput", OPT_INT32, &inst_fetch_throughput, - "the number of fetched intruction per warp each cycle", - "1"); - option_parser_register(opp, "-gpgpu_reg_file_port_throughput", OPT_INT32, ®_file_port_throughput, - "the number ports of the register file", - "1"); - //used for trace-driven mode - option_parser_register(opp, "-trace_opcode_latency_initiation_int", OPT_CSTR, &trace_opcode_latency_initiation_int, - "Opcode latencies and initiation for integers in trace driven mode <latency,initiation>", - "4,1"); - option_parser_register(opp, "-trace_opcode_latency_initiation_sp", OPT_CSTR, &trace_opcode_latency_initiation_sp, - "Opcode latencies and initiation for sp in trace driven mode <latency,initiation>", - "4,1"); - option_parser_register(opp, "-trace_opcode_latency_initiation_dp", OPT_CSTR, &trace_opcode_latency_initiation_dp, - "Opcode latencies and initiation for dp in trace driven mode <latency,initiation>", - "4,1"); - option_parser_register(opp, "-trace_opcode_latency_initiation_sfu", OPT_CSTR, &trace_opcode_latency_initiation_sfu, - "Opcode latencies and initiation for sfu in trace driven mode <latency,initiation>", - "4,1"); - option_parser_register(opp, "-trace_opcode_latency_initiation_tensor", OPT_CSTR, &trace_opcode_latency_initiation_tensor, - "Opcode latencies and initiation for tensor in trace driven mode <latency,initiation>", - "4,1"); + option_parser_register(opp, "-gpgpu_perfect_inst_const_cache", OPT_BOOL, + &perfect_inst_const_cache, + "perfect inst and const cache mode, so all inst and " + "const hits in the cache(default = disabled)", + "0"); + option_parser_register( + opp, "-gpgpu_inst_fetch_throughput", OPT_INT32, &inst_fetch_throughput, + "the number of fetched intruction per warp each cycle", "1"); + option_parser_register(opp, "-gpgpu_reg_file_port_throughput", OPT_INT32, + ®_file_port_throughput, + "the number ports of the register file", "1"); + // used for trace-driven mode + option_parser_register(opp, "-trace_opcode_latency_initiation_int", OPT_CSTR, + &trace_opcode_latency_initiation_int, + "Opcode latencies and initiation for integers in " + "trace driven mode <latency,initiation>", + "4,1"); + option_parser_register(opp, "-trace_opcode_latency_initiation_sp", OPT_CSTR, + &trace_opcode_latency_initiation_sp, + "Opcode latencies and initiation for sp in trace " + "driven mode <latency,initiation>", + "4,1"); + option_parser_register(opp, "-trace_opcode_latency_initiation_dp", OPT_CSTR, + &trace_opcode_latency_initiation_dp, + "Opcode latencies and initiation for dp in trace " + "driven mode <latency,initiation>", + "4,1"); + option_parser_register(opp, "-trace_opcode_latency_initiation_sfu", OPT_CSTR, + &trace_opcode_latency_initiation_sfu, + "Opcode latencies and initiation for sfu in trace " + "driven mode <latency,initiation>", + "4,1"); + option_parser_register(opp, "-trace_opcode_latency_initiation_tensor", + OPT_CSTR, &trace_opcode_latency_initiation_tensor, + "Opcode latencies and initiation for tensor in trace " + "driven mode <latency,initiation>", + "4,1"); } void gpgpu_sim_config::reg_options(option_parser_t opp) { @@ -642,21 +662,21 @@ void gpgpu_sim_config::reg_options(option_parser_t opp) { &(gpgpu_ctx->device_runtime->g_cdp_enabled), "Turn on CDP", "0"); - option_parser_register(opp, "-gpgpu_TB_launch_latency", OPT_INT32, - &(gpgpu_ctx->device_runtime->g_TB_launch_latency), "thread block launch latency in cycles. Default: 0", - "0"); + option_parser_register(opp, "-gpgpu_TB_launch_latency", OPT_INT32, + &(gpgpu_ctx->device_runtime->g_TB_launch_latency), + "thread block launch latency in cycles. Default: 0", + "0"); - //Trace driven mode parameters - option_parser_register(opp, "-trace_driven_mode", OPT_BOOL, - &trace_driven_mode, "Turn on trace_driven_mode", - "0"); - option_parser_register(opp, "-trace_skip_first_kernel", OPT_BOOL, - &trace_skip_first_kernel, "skip first intiliztion kernel in trace mode", - "0"); - option_parser_register(opp, "-trace", OPT_CSTR, - &g_traces_filename, "traces kernel file" - "traces kernel file directory", - "./traces/kernelslist.g"); + // Trace driven mode parameters + option_parser_register(opp, "-trace_driven_mode", OPT_BOOL, + &trace_driven_mode, "Turn on trace_driven_mode", "0"); + option_parser_register(opp, "-trace_skip_first_kernel", OPT_BOOL, + &trace_skip_first_kernel, + "skip first intiliztion kernel in trace mode", "0"); + option_parser_register(opp, "-trace", OPT_CSTR, &g_traces_filename, + "traces kernel file" + "traces kernel file directory", + "./traces/kernelslist.g"); } ///////////////////////////////////////////////////////////////////////////// @@ -733,18 +753,17 @@ bool gpgpu_sim::get_more_cta_left() const { return false; } -void gpgpu_sim::decrement_kernel_latency() -{ - for(unsigned n=0; n < m_running_kernels.size(); n++ ) { - if( m_running_kernels[n] && m_running_kernels[n]->m_kernel_TB_latency ) - m_running_kernels[n]->m_kernel_TB_latency--; - } +void gpgpu_sim::decrement_kernel_latency() { + for (unsigned n = 0; n < m_running_kernels.size(); n++) { + if (m_running_kernels[n] && m_running_kernels[n]->m_kernel_TB_latency) + m_running_kernels[n]->m_kernel_TB_latency--; + } } kernel_info_t *gpgpu_sim::select_kernel() { if (m_running_kernels[m_last_issued_kernel] && - !m_running_kernels[m_last_issued_kernel]->no_more_ctas_to_run() && - !m_running_kernels[m_last_issued_kernel]->m_kernel_TB_latency) { + !m_running_kernels[m_last_issued_kernel]->no_more_ctas_to_run() && + !m_running_kernels[m_last_issued_kernel]->m_kernel_TB_latency) { unsigned launch_uid = m_running_kernels[m_last_issued_kernel]->get_uid(); if (std::find(m_executed_kernel_uids.begin(), m_executed_kernel_uids.end(), launch_uid) == m_executed_kernel_uids.end()) { @@ -760,8 +779,8 @@ kernel_info_t *gpgpu_sim::select_kernel() { for (unsigned n = 0; n < m_running_kernels.size(); n++) { unsigned idx = (n + m_last_issued_kernel + 1) % m_config.max_concurrent_kernel; - if( kernel_more_cta_left(m_running_kernels[idx]) && - !m_running_kernels[idx]->m_kernel_TB_latency){ + if (kernel_more_cta_left(m_running_kernels[idx]) && + !m_running_kernels[idx]->m_kernel_TB_latency) { m_last_issued_kernel = idx; m_running_kernels[idx]->start_cycle = gpu_sim_cycle + gpu_tot_sim_cycle; // record this kernel for stat print if it is the first time this kernel @@ -1630,15 +1649,15 @@ void shader_core_ctx::issue_block2core(kernel_info_t &kernel) { for (unsigned i = start_thread; i < end_thread; i++) { m_threadState[i].m_cta_id = free_cta_hw_id; unsigned warp_id = i / m_config->warp_size; - if(m_gpu->get_config().is_trace_driven_mode()) { - trace_shader_core_ctx* trace_core = static_cast<trace_shader_core_ctx*> (this); - nthreads_in_block += trace_core->trace_sim_inc_thread(kernel); - } - else - nthreads_in_block += ptx_sim_init_thread( - kernel, &m_thread[i], m_sid, i, cta_size - (i - start_thread), - m_config->n_thread_per_shader, this, free_cta_hw_id, warp_id, - m_cluster->get_gpu()); + if (m_gpu->get_config().is_trace_driven_mode()) { + trace_shader_core_ctx *trace_core = + static_cast<trace_shader_core_ctx *>(this); + nthreads_in_block += trace_core->trace_sim_inc_thread(kernel); + } else + nthreads_in_block += ptx_sim_init_thread( + kernel, &m_thread[i], m_sid, i, cta_size - (i - start_thread), + m_config->n_thread_per_shader, this, free_cta_hw_id, warp_id, + m_cluster->get_gpu()); m_threadState[i].m_active = true; // load thread local memory and register file if (m_gpu->resume_option == 1 && kernel.get_uid() == m_gpu->resume_kernel && @@ -1673,7 +1692,7 @@ void shader_core_ctx::issue_block2core(kernel_info_t &kernel) { m_barriers.allocate_barrier(free_cta_hw_id, warps); // initialize the SIMT stacks and fetch hardware - init_warps( free_cta_hw_id, start_thread, end_thread, ctaid, cta_size, kernel); + init_warps(free_cta_hw_id, start_thread, end_thread, ctaid, cta_size, kernel); m_n_active_cta++; shader_CTA_count_log(m_sid, 1); @@ -1865,7 +1884,7 @@ void gpgpu_sim::cycle() { #endif issue_block2core(); - decrement_kernel_latency(); + decrement_kernel_latency(); // Depending on configuration, invalidate the caches once all of threads are // completed. @@ -1978,8 +1997,9 @@ void shader_core_ctx::dump_warp_state(FILE *fout) const { void gpgpu_sim::perf_memcpy_to_gpu(size_t dst_start_addr, size_t count) { if (m_memory_config->m_perf_sim_memcpy) { - //if(!m_config.trace_driven_mode) //in trace-driven mode, CUDA runtime can start nre data structure at any position - // assert (dst_start_addr % 32 == 0); + // if(!m_config.trace_driven_mode) //in trace-driven mode, CUDA runtime + // can start nre data structure at any position assert (dst_start_addr % 32 + //== 0); for (unsigned counter = 0; counter < count; counter += 32) { const unsigned wr_addr = dst_start_addr + counter; |