1 files changed, 33 insertions, 16 deletions

diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 3b2b17c..8eb3f28 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -3313,26 +3313,37 @@ bool ldst_unit::shared_cycle(warp_inst_t &inst, mem_stage_stall_type &rc_fail,
 
   bool any_stall = false;
 
-  // Primary's own cycles (only counts if primary is shared).
-  if (primary_is_shared) {
-    if (inst.has_dispatch_delay()) {
+  // MEMCO v3 Model B: when unified bank-conflict cycles are active for
+  // this composite, replace the per-set max with a single unified counter
+  // (computed at ldst_unit::issue across the union of all participating
+  // lanes). Skip the primary + per-set walks below.
+  if (inst.unified_shared_active()) {
+    if (inst.has_dispatch_delay_unified()) {
       m_stats->gpgpu_n_shmem_bank_access[m_sid]++;
     }
-    if (inst.dispatch_delay()) any_stall = true;
-  }
-
-  // Per-set cycles for shared coissuer sets. Each set's cycles counts
-  // down independently; we stall as long as ANY still has cycles > 0.
-  if (inst.has_simd_sets()) {
-    std::vector<simd_set_info> &sets = inst.get_simd_sets_mutable();
-    for (unsigned s = 0; s < sets.size(); s++) {
-      if (!sets[s].valid || sets[s].source_inst == NULL) continue;
-      enum _memory_space_t src_sp = sets[s].source_inst->space.get_type();
-      if (src_sp != shared_space && src_sp != sstarr_space) continue;
-      if (sets[s].has_dispatch_delay()) {
+    if (inst.dispatch_delay_unified()) any_stall = true;
+  } else {
+    // Primary's own cycles (only counts if primary is shared).
+    if (primary_is_shared) {
+      if (inst.has_dispatch_delay()) {
         m_stats->gpgpu_n_shmem_bank_access[m_sid]++;
       }
-      if (sets[s].dispatch_delay()) any_stall = true;
+      if (inst.dispatch_delay()) any_stall = true;
+    }
+
+    // Per-set cycles for shared coissuer sets. Each set's cycles counts
+    // down independently; we stall as long as ANY still has cycles > 0.
+    if (inst.has_simd_sets()) {
+      std::vector<simd_set_info> &sets = inst.get_simd_sets_mutable();
+      for (unsigned s = 0; s < sets.size(); s++) {
+        if (!sets[s].valid || sets[s].source_inst == NULL) continue;
+        enum _memory_space_t src_sp = sets[s].source_inst->space.get_type();
+        if (src_sp != shared_space && src_sp != sstarr_space) continue;
+        if (sets[s].has_dispatch_delay()) {
+          m_stats->gpgpu_n_shmem_bank_access[m_sid]++;
+        }
+        if (sets[s].dispatch_delay()) any_stall = true;
+      }
     }
   }
 
@@ -4308,6 +4319,12 @@ void ldst_unit::issue(register_set &reg_set) {
     coalesce_accessq_across_sets(*inst);
   }
 
+  // MEMCO v3 Model B: compute unified shared bank-conflict cycles across
+  // all participating sets when MEMCOV3_SHARED_UNIFIED is set.
+  if (is_coissue_composite) {
+    inst->compute_unified_shared_cycles();
+  }
+
   if (is_coissue_composite) {
     // MEM co-issue: accesses in the composite's queue may originate from
     // different source warps (inter-warp) or different splits of the same