1 files changed, 85 insertions, 19 deletions

diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 0897107..ea2d9b3 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -4680,24 +4680,53 @@ unsigned register_bank(int regnum, int wid, unsigned num_banks,
 bool opndcoll_rfu_t::writeback(warp_inst_t &inst) {
   assert(!inst.empty());
 
+  unsigned sched_id = inst.get_schd_id();
+
+  // Phase 1: Primary warp's destination registers
   std::list<unsigned> regs = m_shader->get_regs_written(inst);
   for (unsigned op = 0; op < MAX_REG_OPERANDS; op++) {
-    int reg_num = inst.arch_reg.dst[op];  // this math needs to match that used
-                                          // in function_info::ptx_decode_inst
-    if (reg_num >= 0) {                   // valid register
+    int reg_num = inst.arch_reg.dst[op];
+    if (reg_num >= 0) {
       unsigned bank =
           register_bank(reg_num, inst.warp_id(), m_num_banks, sub_core_model,
-                        m_num_banks_per_sched, inst.get_schd_id());
+                        m_num_banks_per_sched, sched_id);
       if (m_arbiter.bank_idle(bank)) {
         m_arbiter.allocate_bank_for_write(
             bank, op_t(&inst, reg_num, m_num_banks, sub_core_model,
-                       m_num_banks_per_sched, inst.get_schd_id()));
+                       m_num_banks_per_sched, sched_id));
         inst.arch_reg.dst[op] = -1;
       } else {
         return false;
       }
     }
   }
+
+  // Phase 2: Co-issued sets' destination registers (different instructions)
+  if (inst.has_simd_sets()) {
+    const std::vector<simd_set_info> &sets = inst.get_simd_sets();
+    for (unsigned s = 0; s < sets.size(); s++) {
+      if (!sets[s].valid) continue;
+      if (sets[s].warp_id == inst.warp_id()) continue;
+      if (sets[s].source_inst == NULL) continue;
+
+      for (unsigned op = 0; op < MAX_REG_OPERANDS; op++) {
+        int reg_num = sets[s].source_inst->arch_reg.dst[op];
+        if (reg_num >= 0) {
+          unsigned bank = register_bank(reg_num, sets[s].warp_id, m_num_banks,
+                                        sub_core_model, m_num_banks_per_sched,
+                                        sched_id);
+          if (m_arbiter.bank_idle(bank)) {
+            m_arbiter.allocate_bank_for_write(
+                bank, op_t(sets[s].warp_id, reg_num, m_num_banks,
+                           sub_core_model, m_num_banks_per_sched, sched_id));
+          } else {
+            return false;
+          }
+        }
+      }
+    }
+  }
+
   for (unsigned i = 0; i < (unsigned)regs.size(); i++) {
     if (m_shader->get_config()->gpgpu_clock_gated_reg_file) {
       unsigned active_count = 0;
@@ -4714,7 +4743,7 @@ bool opndcoll_rfu_t::writeback(warp_inst_t &inst) {
       m_shader->incregfile_writes(active_count);
     } else {
       m_shader->incregfile_writes(
-          m_shader->get_config()->warp_size);  // inst.active_count());
+          m_shader->get_config()->warp_size);
     }
   }
   return true;
@@ -4875,26 +4904,63 @@ bool opndcoll_rfu_t::collector_unit_t::allocate(register_set *pipeline_reg_set,
   warp_inst_t **pipeline_reg = pipeline_reg_set->get_ready();
   if ((pipeline_reg) and !((*pipeline_reg)->empty())) {
     m_warp_id = (*pipeline_reg)->warp_id();
-    std::vector<int> prev_regs;  // remove duplicate regs within same instr
+    m_has_simd_sets = (*pipeline_reg)->has_simd_sets();
+    unsigned sched_id = (*pipeline_reg)->get_schd_id();
+    unsigned op_idx = 0;
+
+    // Phase 1: Primary warp's source registers
+    std::vector<int> prev_regs;
     for (unsigned op = 0; op < MAX_REG_OPERANDS; op++) {
-      int reg_num =
-          (*pipeline_reg)
-              ->arch_reg.src[op];  // this math needs to match that used in
-                                   // function_info::ptx_decode_inst
+      int reg_num = (*pipeline_reg)->arch_reg.src[op];
       bool new_reg = true;
       for (auto r : prev_regs) {
         if (r == reg_num) new_reg = false;
       }
-      if (reg_num >= 0 && new_reg) {  // valid register
+      if (reg_num >= 0 && new_reg) {
         prev_regs.push_back(reg_num);
-        m_src_op[op] =
-            op_t(this, op, reg_num, m_num_banks, m_sub_core_model,
-                 m_num_banks_per_sched, (*pipeline_reg)->get_schd_id());
-        m_not_ready.set(op);
-      } else
-        m_src_op[op] = op_t();
+        m_src_op[op_idx] =
+            op_t(this, op_idx, reg_num, m_num_banks, m_sub_core_model,
+                 m_num_banks_per_sched, sched_id);
+        m_not_ready.set(op_idx);
+      } else {
+        m_src_op[op_idx] = op_t();
+      }
+      op_idx++;
     }
-    // move_warp(m_warp,*pipeline_reg);
+
+    // Phase 2: Co-issued sets' source registers (different instructions)
+    if (m_has_simd_sets) {
+      const std::vector<simd_set_info> &sets =
+          (*pipeline_reg)->get_simd_sets();
+      for (unsigned s = 0; s < sets.size(); s++) {
+        if (!sets[s].valid) continue;
+        if (sets[s].warp_id == m_warp_id) continue;
+        if (sets[s].source_inst == NULL) continue;
+
+        std::vector<int> set_prev_regs;
+        for (unsigned op = 0; op < MAX_REG_OPERANDS && op_idx < MAX_REG_OPERANDS * 2; op++) {
+          int reg_num = sets[s].source_inst->arch_reg.src[op];
+          bool new_reg = true;
+          for (auto r : set_prev_regs) {
+            if (r == reg_num) new_reg = false;
+          }
+          if (reg_num >= 0 && new_reg) {
+            set_prev_regs.push_back(reg_num);
+            m_src_op[op_idx] =
+                op_t(this, op_idx, reg_num, m_num_banks, m_sub_core_model,
+                     m_num_banks_per_sched, sched_id, sets[s].warp_id);
+            m_not_ready.set(op_idx);
+            op_idx++;
+          }
+        }
+      }
+    }
+
+    // Clear remaining slots
+    for (; op_idx < MAX_REG_OPERANDS * 2; op_idx++) {
+      m_src_op[op_idx] = op_t();
+    }
+
     pipeline_reg_set->move_out_to(m_warp);
     return true;
   }