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-rw-r--r--src/gpgpu-sim/shader.cc155
1 files changed, 84 insertions, 71 deletions
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index c365ebb..6a0e3d6 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -1659,35 +1659,46 @@ mem_stage_stall_type ldst_unit::process_memory_access_queue_l1cache( l1_cache *c
if( inst.accessq_empty() )
return result;
- mem_fetch *mf = m_mf_allocator->alloc(inst,inst.accessq_back(),m_core->get_gpu()->gpu_sim_cycle+m_core->get_gpu()->gpu_tot_sim_cycle);
-
if(m_config->m_L1D_config.l1_latency > 0)
{
- if((l1_latency_queue[m_config->m_L1D_config.l1_latency-1]) == NULL)
- {
- l1_latency_queue[m_config->m_L1D_config.l1_latency-1] = mf;
+ for(int j=0; j<m_config->m_L1D_config.l1_banks; j++) { //We can handle at max l1_banks reqs per cycle
- if( mf->get_inst().is_store() ) {
- unsigned inc_ack = (m_config->m_L1D_config.get_mshr_type() == SECTOR_ASSOC)?
- (mf->get_data_size()/SECTOR_SIZE) : 1;
+ if( inst.accessq_empty() )
+ return result;
- for(unsigned i=0; i< inc_ack; ++i)
- m_core->inc_store_req( inst.warp_id() );
- }
+ mem_fetch *mf = m_mf_allocator->alloc(inst,inst.accessq_back(),m_core->get_gpu()->gpu_sim_cycle+m_core->get_gpu()->gpu_tot_sim_cycle);
+ unsigned bank_id = m_config->m_L1D_config.set_bank(mf->get_addr());
+ assert(bank_id < m_config->m_L1D_config.l1_banks);
+
+ if((l1_latency_queue[bank_id][m_config->m_L1D_config.l1_latency-1]) == NULL)
+ {
+ l1_latency_queue[bank_id][m_config->m_L1D_config.l1_latency-1] = mf;
+
+ if( mf->get_inst().is_store() ) {
+ unsigned inc_ack = (m_config->m_L1D_config.get_mshr_type() == SECTOR_ASSOC)?
+ (mf->get_data_size()/SECTOR_SIZE) : 1;
+
+ for(unsigned i=0; i< inc_ack; ++i)
+ m_core->inc_store_req( inst.warp_id() );
+ }
- inst.accessq_pop_back();
+ inst.accessq_pop_back();
+ }
+ else
+ {
+ result = BK_CONF;
+ delete mf;
+ break; //do not try again, just break from the loop and try the next cycle
+ }
}
- else
- {
- result = BK_CONF;
- delete mf;
- }
- if( !inst.accessq_empty() && result !=BK_CONF)
+ if( !inst.accessq_empty() && result !=BK_CONF)
result = COAL_STALL;
- return result;
+
+ return result;
}
else
{
+ mem_fetch *mf = m_mf_allocator->alloc(inst,inst.accessq_back(),m_core->get_gpu()->gpu_sim_cycle+m_core->get_gpu()->gpu_tot_sim_cycle);
std::list<cache_event> events;
enum cache_request_status status = cache->access(mf->get_addr(),mf,m_core->get_gpu()->gpu_sim_cycle+m_core->get_gpu()->gpu_tot_sim_cycle,events);
return process_cache_access( cache, mf->get_addr(), inst, events, mf, status );
@@ -1696,63 +1707,64 @@ mem_stage_stall_type ldst_unit::process_memory_access_queue_l1cache( l1_cache *c
void ldst_unit::L1_latency_queue_cycle()
{
- //std::deque< std::pair<mem_fetch*,bool> >::iterator it = m_latency_queue.begin();
- if((l1_latency_queue[0]) != NULL)
- {
- mem_fetch* mf_next = l1_latency_queue[0];
- std::list<cache_event> events;
- enum cache_request_status status = m_L1D->access(mf_next->get_addr(),mf_next,m_core->get_gpu()->gpu_sim_cycle+m_core->get_gpu()->gpu_tot_sim_cycle,events);
+ for(int j=0; j<m_config->m_L1D_config.l1_banks; j++) {
+ if((l1_latency_queue[j][0]) != NULL)
+ {
+ mem_fetch* mf_next = l1_latency_queue[j][0];
+ std::list<cache_event> events;
+ enum cache_request_status status = m_L1D->access(mf_next->get_addr(),mf_next,m_core->get_gpu()->gpu_sim_cycle+m_core->get_gpu()->gpu_tot_sim_cycle,events);
- bool write_sent = was_write_sent(events);
- bool read_sent = was_read_sent(events);
+ bool write_sent = was_write_sent(events);
+ bool read_sent = was_read_sent(events);
- if ( status == HIT ) {
- assert( !read_sent );
- l1_latency_queue[0] = NULL;
- if ( mf_next->get_inst().is_load() ) {
- for ( unsigned r=0; r < MAX_OUTPUT_VALUES; r++)
- if (mf_next->get_inst().out[r] > 0)
- {
- assert(m_pending_writes[mf_next->get_inst().warp_id()][mf_next->get_inst().out[r]]>0);
- unsigned still_pending = --m_pending_writes[mf_next->get_inst().warp_id()][mf_next->get_inst().out[r]];
- if(!still_pending)
+ if ( status == HIT ) {
+ assert( !read_sent );
+ l1_latency_queue[j][0] = NULL;
+ if ( mf_next->get_inst().is_load() ) {
+ for ( unsigned r=0; r < MAX_OUTPUT_VALUES; r++)
+ if (mf_next->get_inst().out[r] > 0)
{
- m_pending_writes[mf_next->get_inst().warp_id()].erase(mf_next->get_inst().out[r]);
- m_scoreboard->releaseRegister(mf_next->get_inst().warp_id(),mf_next->get_inst().out[r]);
- m_core->warp_inst_complete(mf_next->get_inst());
+ assert(m_pending_writes[mf_next->get_inst().warp_id()][mf_next->get_inst().out[r]]>0);
+ unsigned still_pending = --m_pending_writes[mf_next->get_inst().warp_id()][mf_next->get_inst().out[r]];
+ if(!still_pending)
+ {
+ m_pending_writes[mf_next->get_inst().warp_id()].erase(mf_next->get_inst().out[r]);
+ m_scoreboard->releaseRegister(mf_next->get_inst().warp_id(),mf_next->get_inst().out[r]);
+ m_core->warp_inst_complete(mf_next->get_inst());
+ }
}
- }
- }
+ }
- //For write hit in WB policy
- if(mf_next->get_inst().is_store() && !write_sent)
- {
- unsigned dec_ack = (m_config->m_L1D_config.get_mshr_type() == SECTOR_ASSOC)?
- (mf_next->get_data_size()/SECTOR_SIZE) : 1;
+ //For write hit in WB policy
+ if(mf_next->get_inst().is_store() && !write_sent)
+ {
+ unsigned dec_ack = (m_config->m_L1D_config.get_mshr_type() == SECTOR_ASSOC)?
+ (mf_next->get_data_size()/SECTOR_SIZE) : 1;
- mf_next->set_reply();
+ mf_next->set_reply();
- for(unsigned i=0; i< dec_ack; ++i)
- m_core->store_ack(mf_next);
- }
+ for(unsigned i=0; i< dec_ack; ++i)
+ m_core->store_ack(mf_next);
+ }
- if( !write_sent )
- delete mf_next;
+ if( !write_sent )
+ delete mf_next;
- } else if ( status == RESERVATION_FAIL ) {
- assert( !read_sent );
- assert( !write_sent );
- } else {
- assert( status == MISS || status == HIT_RESERVED );
- l1_latency_queue[0] = NULL;
- }
- }
+ } else if ( status == RESERVATION_FAIL ) {
+ assert( !read_sent );
+ assert( !write_sent );
+ } else {
+ assert( status == MISS || status == HIT_RESERVED );
+ l1_latency_queue[j][0] = NULL;
+ }
+ }
- for( unsigned stage = 0; stage<m_config->m_L1D_config.l1_latency-1; ++stage)
- if( l1_latency_queue[stage] == NULL) {
- l1_latency_queue[stage] = l1_latency_queue[stage+1] ;
- l1_latency_queue[stage+1] = NULL;
- }
+ for( unsigned stage = 0; stage<m_config->m_L1D_config.l1_latency-1; ++stage)
+ if( l1_latency_queue[j][stage] == NULL) {
+ l1_latency_queue[j][stage] = l1_latency_queue[j][stage+1] ;
+ l1_latency_queue[j][stage+1] = NULL;
+ }
+ }
}
@@ -2132,11 +2144,12 @@ ldst_unit::ldst_unit( mem_fetch_interface *icnt,
IN_L1D_MISS_QUEUE,
core->get_gpu());
- if(m_config->m_L1D_config.l1_latency > 0)
- {
- for(unsigned i = 0; i < m_config->m_L1D_config.l1_latency; i++ )
- l1_latency_queue.push_back((mem_fetch*)NULL);
- }
+ l1_latency_queue.resize(m_config->m_L1D_config.l1_banks);
+ assert(m_config->m_L1D_config.l1_latency > 0);
+
+ for(unsigned j = 0; j < m_config->m_L1D_config.l1_banks; j++ )
+ l1_latency_queue[j].resize(m_config->m_L1D_config.l1_latency,(mem_fetch*)NULL);
+
}
m_name = "MEM ";
}
generated by cgit v1.3 (git 2.53.0) at 2026-07-10 23:44:04 +0000