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-rw-r--r--src/gpgpu-sim/dram.cc29
-rw-r--r--src/gpgpu-sim/dram.h10
-rw-r--r--src/gpgpu-sim/gpu-sim.cc4
-rw-r--r--src/gpgpu-sim/gpu-sim.h22
-rw-r--r--src/gpgpu-sim/shader.cc17
5 files changed, 72 insertions, 10 deletions
diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc
index 104ec66..c073f0d 100644
--- a/src/gpgpu-sim/dram.cc
+++ b/src/gpgpu-sim/dram.cc
@@ -56,13 +56,24 @@ dram_t::dram_t( unsigned int partition_id, const struct memory_config *config, m
rw = READ; //read mode is default
+ bkgrp = (bankgrp_t**) calloc(sizeof(bankgrp_t*), m_config->nbkgrp);
+ bkgrp[0] = (bankgrp_t*) calloc(sizeof(bank_t), m_config->nbkgrp);
+ for (unsigned i=1; i<m_config->nbkgrp; i++) {
+ bkgrp[i] = bkgrp[0] + i;
+ }
+ for (unsigned i=0; i<m_config->nbkgrp; i++) {
+ bkgrp[i]->CCDLc = 0;
+ bkgrp[i]->RTPLc = 0;
+ }
+
bk = (bank_t**) calloc(sizeof(bank_t*),m_config->nbk);
bk[0] = (bank_t*) calloc(sizeof(bank_t),m_config->nbk);
for (unsigned i=1;i<m_config->nbk;i++)
bk[i] = bk[0] + i;
- for (unsigned i=0;i<m_config->nbk;i++)
+ for (unsigned i=0;i<m_config->nbk;i++) {
bk[i]->state = BANK_IDLE;
-
+ bk[i]->bkgrpindex = i/(m_config->nbk/m_config->nbkgrp);
+ }
prio = 0;
rwq = new fifo_pipeline<dram_req_t>("rwq",m_config->CL,m_config->CL+1);
mrqq = new fifo_pipeline<dram_req_t>("mrqq",0,2);
@@ -248,10 +259,12 @@ void dram_t::cycle()
// check if any bank is ready to issue a new read
for (unsigned i=0;i<m_config->nbk;i++) {
unsigned j = (i + prio) % m_config->nbk;
+ unsigned grp = j>>m_config->bk_tag_length;
if (bk[j]->mrq) { //if currently servicing a memory request
bk[j]->mrq->data->set_status(IN_PARTITION_DRAM,gpu_sim_cycle+gpu_tot_sim_cycle);
// correct row activated for a READ
if ( !issued && !CCDc && !bk[j]->RCDc &&
+ !(bkgrp[grp]->CCDLc) &&
(bk[j]->curr_row == bk[j]->mrq->row) &&
(bk[j]->mrq->rw == READ) && (WTRc == 0 ) &&
(bk[j]->state == BANK_ACTIVE) &&
@@ -263,8 +276,10 @@ void dram_t::cycle()
rwq->push(bk[j]->mrq);
bk[j]->mrq->txbytes += m_config->BL * m_config->busW * m_config->gpu_n_mem_per_ctrlr; //16 bytes
CCDc = m_config->tCCD;
+ bkgrp[grp]->CCDLc = m_config->tCCDL;
RTWc = m_config->tRTW;
bk[j]->RTPc = m_config->BL/2;
+ bkgrp[grp]->RTPLc = m_config->tRTPL;
issued = true;
n_rd++;
bwutil+= m_config->BL/2;
@@ -283,6 +298,7 @@ void dram_t::cycle()
} else
// correct row activated for a WRITE
if ( !issued && !CCDc && !bk[j]->RCDWRc &&
+ !(bkgrp[grp]->CCDLc) &&
(bk[j]->curr_row == bk[j]->mrq->row) &&
(bk[j]->mrq->rw == WRITE) && (RTWc == 0 ) &&
(bk[j]->state == BANK_ACTIVE) &&
@@ -295,6 +311,7 @@ void dram_t::cycle()
bk[j]->mrq->txbytes += m_config->BL * m_config->busW * m_config->gpu_n_mem_per_ctrlr; /*16 bytes*/
CCDc = m_config->tCCD;
+ bkgrp[grp]->CCDLc = m_config->tCCDL;
WTRc = m_config->tWTR;
bk[j]->WTPc = m_config->tWTP;
issued = true;
@@ -342,7 +359,9 @@ void dram_t::cycle()
if ( (!issued) &&
(bk[j]->curr_row != bk[j]->mrq->row) &&
(bk[j]->state == BANK_ACTIVE) &&
- (!bk[j]->RASc && !bk[j]->WTPc && !bk[j]->RTPc) ) {
+ (!bk[j]->RASc && !bk[j]->WTPc &&
+ !bk[j]->RTPc &&
+ !bkgrp[grp]->RTPLc) ) {
// make the bank idle again
bk[j]->state = BANK_IDLE;
bk[j]->RPc = m_config->tRP;
@@ -389,6 +408,10 @@ void dram_t::cycle()
DEC2ZERO(bk[j]->WTPc);
DEC2ZERO(bk[j]->RTPc);
}
+ for (unsigned j=0; j<m_config->nbkgrp; j++) {
+ DEC2ZERO(bkgrp[j]->CCDLc);
+ DEC2ZERO(bkgrp[j]->RTPLc);
+ }
#ifdef DRAM_VISUALIZE
visualize();
diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h
index 96b912b..ad773b3 100644
--- a/src/gpgpu-sim/dram.h
+++ b/src/gpgpu-sim/dram.h
@@ -58,6 +58,12 @@ public:
class mem_fetch * data;
};
+struct bankgrp_t
+{
+ unsigned int CCDLc;
+ unsigned int RTPLc;
+};
+
struct bank_t
{
unsigned int RCDc;
@@ -77,6 +83,8 @@ struct bank_t
unsigned int n_access;
unsigned int n_writes;
unsigned int n_idle;
+
+ unsigned int bkgrpindex;
};
struct mem_fetch;
@@ -110,6 +118,8 @@ private:
const struct memory_config *m_config;
+ bankgrp_t **bkgrp;
+
bank_t **bk;
unsigned int prio;
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 51b832c..e71818b 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -123,8 +123,8 @@ void memory_config::reg_options(class OptionParser * opp)
"Burst length of each DRAM request (default = 4 DDR cycle)",
"4");
option_parser_register(opp, "-gpgpu_dram_timing_opt", OPT_CSTR, &gpgpu_dram_timing_opt,
- "DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR}",
- "4:2:8:12:21:13:34:9:4:5:13");
+ "DRAM timing parameters = {nbk:nbkgrp:tCCD:tCCDL:tRRD:tRCD:tRAS:tRP:tRTPL:tRC:CL:WL:tCDLR:tWR}",
+ "4:1:2:0:8:12:21:13:0:34:9:4:5:13");
option_parser_register(opp, "-rop_latency", OPT_UINT32, &rop_latency,
"ROP queue latency (default 85)",
"85");
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index 31def4b..fe66d04 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -72,8 +72,14 @@ struct memory_config {
void init()
{
assert(gpgpu_dram_timing_opt);
- sscanf(gpgpu_dram_timing_opt,"%d:%d:%d:%d:%d:%d:%d:%d:%d:%d:%d",
- &nbk,&tCCD,&tRRD,&tRCD,&tRAS,&tRP,&tRC,&CL,&WL,&tCDLR,&tWR);
+ sscanf(gpgpu_dram_timing_opt,"%d:%d:%d:%d:%d:%d:%d:%d:%d:%d:%d:%d:%d:%d",
+ &nbk,&nbkgrp,&tCCD,&tCCDL,&tRRD,&tRCD,&tRAS,&tRP,&tRTPL,&tRC,&CL,&WL,&tCDLR,&tWR);
+ int nbkt = nbk/nbkgrp;
+ unsigned i;
+ for (i=0; nbkt>0; i++) {
+ nbkt = nbkt>>1;
+ }
+ bk_tag_length = i;
tRCDWR = tRCD-(WL+1);
tRTW = (CL+(BL/2)+2-WL);
tWTR = (WL+(BL/2)+tCDLR);
@@ -101,6 +107,10 @@ struct memory_config {
unsigned dram_latency;
// DRAM parameters
+
+ unsigned tCCDL; //column to column delay when bank groups are enabled
+ unsigned tRTPL; //read to precharge delay when bank groups are enabled for GDDR5 this is identical to RTPS, if for other DRAM this is different, you will need to split them in two
+
unsigned tCCD; //column to column delay
unsigned tRRD; //minimal time required between activation of rows in different banks
unsigned tRCD; //row to column delay - time required to activate a row before a read
@@ -119,6 +129,9 @@ struct memory_config {
unsigned tWTP; //time to switch from write to precharge in the same bank
unsigned busW;
+ unsigned nbkgrp; // number of bank groups (has to be power of 2)
+ unsigned bk_tag_length; //number of bits that define a bank inside a bank group
+
unsigned nbk;
linear_to_raw_address_translation m_address_mapping;
@@ -237,7 +250,7 @@ public:
const gpgpu_sim_config &get_config() const { return m_config; }
void gpu_print_stat() const;
void dump_pipeline( int mask, int s, int m ) const;
-
+
//The next three functions added to be used by the functional simulation function
//! Get shader core configuration
@@ -270,6 +283,7 @@ private:
void shader_print_runtime_stat( FILE *fout );
void shader_print_l1_miss_stat( FILE *fout ) const;
void visualizer_printstat();
+ void print_shader_cycle_distro( FILE *fout ) const;
void gpgpu_debug();
@@ -311,7 +325,7 @@ public:
unsigned long long gpu_sim_insn;
unsigned long long gpu_tot_sim_insn;
unsigned long long gpu_sim_insn_last_update;
- unsigned gpu_sim_insn_last_update_sid;
+ unsigned gpu_sim_insn_last_update_sid;
};
#endif
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 4c90667..527fdcb 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -1736,7 +1736,22 @@ void barrier_set_t::dump() const
void shader_core_ctx::warp_exit( unsigned warp_id )
{
- m_barriers.warp_exit( warp_id );
+ bool done = true;
+ for ( unsigned i = warp_id*get_config()->warp_size;
+ i < (warp_id+1)*get_config()->warp_size;
+ i++ ) {
+
+// if(this->m_thread[i]->m_functional_model_thread_state && this->m_thread[i].m_functional_model_thread_state->donecycle()==0) {
+// done = false;
+// }
+
+
+ if (m_thread[i] && !m_thread[i]->is_done()) done = false;
+ }
+ //if (m_warp[warp_id].get_n_completed() == get_config()->warp_size)
+ //if (this->m_simt_stack[warp_id]->get_num_entries() == 0)
+ if (done)
+ m_barriers.warp_exit( warp_id );
}
bool shader_core_ctx::warp_waiting_at_barrier( unsigned warp_id ) const
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 06:31:31 +0000