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-rw-r--r--src/gpgpu-sim/addrdec.cc2
-rw-r--r--src/gpgpu-sim/dram.cc1
-rw-r--r--src/gpgpu-sim/gpu-cache.h1
-rw-r--r--src/gpgpu-sim/gpu-sim.cc2
-rw-r--r--src/gpgpu-sim/local_interconnect.cc4
-rw-r--r--src/gpgpu-sim/mem_fetch.cc8
-rw-r--r--src/gpgpu-sim/shader.cc139
-rw-r--r--src/gpgpu-sim/shader.h52
-rw-r--r--src/gpgpu-sim/shader_trace.h2
9 files changed, 194 insertions, 17 deletions
diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc
index f4f83f9..db27c82 100644
--- a/src/gpgpu-sim/addrdec.cc
+++ b/src/gpgpu-sim/addrdec.cc
@@ -584,7 +584,7 @@ unsigned next_powerOf2(unsigned n) {
n = n - 1;
// do till only one bit is left
- while (n & n - 1) n = n & (n - 1); // unset rightmost bit
+ while (n & (n - 1)) n = n & (n - 1); // unset rightmost bit
// n is now a power of two (less than n)
diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc
index 662c2ed..53c8238 100644
--- a/src/gpgpu-sim/dram.cc
+++ b/src/gpgpu-sim/dram.cc
@@ -880,4 +880,5 @@ unsigned dram_t::get_bankgrp_number(unsigned i) {
} else {
assert(1);
}
+ return 0; // we should never get here
}
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index aa693b5..ad41320 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -499,6 +499,7 @@ struct sector_cache_block : public cache_block_t {
for (unsigned i = 0; i < SECTOR_CHUNCK_SIZE; ++i) {
if (sector_mask.to_ulong() & (1 << i)) return i;
}
+ return SECTOR_CHUNCK_SIZE; //error
}
};
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index ea50fa0..47c0b4a 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -80,7 +80,7 @@ class gpgpu_sim_wrapper {};
#include <sstream>
#include <string>
-#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+// #define MAX(a, b) (((a) > (b)) ? (a) : (b)) //redefined
bool g_interactive_debugger_enabled = false;
diff --git a/src/gpgpu-sim/local_interconnect.cc b/src/gpgpu-sim/local_interconnect.cc
index df6bd7b..fe7bc74 100644
--- a/src/gpgpu-sim/local_interconnect.cc
+++ b/src/gpgpu-sim/local_interconnect.cc
@@ -148,8 +148,8 @@ void xbar_router::RR_Advance() {
}
}
}
-
- next_node_id = (++next_node_id % total_nodes);
+ next_node_id = next_node_id + 1 ;
+ next_node_id = (next_node_id % total_nodes);
conflicts += conflict_sub;
if (active) {
diff --git a/src/gpgpu-sim/mem_fetch.cc b/src/gpgpu-sim/mem_fetch.cc
index 456d891..0d86046 100644
--- a/src/gpgpu-sim/mem_fetch.cc
+++ b/src/gpgpu-sim/mem_fetch.cc
@@ -84,10 +84,10 @@ mem_fetch::~mem_fetch() { m_status = MEM_FETCH_DELETED; }
#undef MF_TUP_END
void mem_fetch::print(FILE *fp, bool print_inst) const {
- if (this == NULL) {
- fprintf(fp, " <NULL mem_fetch pointer>\n");
- return;
- }
+ // if (this == NULL) { // doenst make sense!
+ // fprintf(fp, " <NULL mem_fetch pointer>\n");
+ // return;
+ // }
fprintf(fp, " mf: uid=%6u, sid%02u:w%02u, part=%u, ", m_request_uid, m_sid,
m_wid, m_raw_addr.chip);
m_access.print(fp);
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index f756aec..67540e0 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -481,7 +481,7 @@ shader_core_ctx::shader_core_ctx(class gpgpu_sim *gpu,
m_config = config;
m_memory_config = mem_config;
m_stats = stats;
- unsigned warp_size = config->warp_size;
+ // unsigned warp_size = config->warp_size;
Issue_Prio = 0;
m_sid = shader_id;
@@ -532,7 +532,6 @@ void shader_core_ctx::reinit(unsigned start_thread, unsigned end_thread,
void shader_core_ctx::init_warps(unsigned cta_id, unsigned start_thread,
unsigned end_thread, unsigned ctaid,
int cta_size, kernel_info_t &kernel) {
- //
address_type start_pc = next_pc(start_thread);
unsigned kernel_id = kernel.get_uid();
if (m_config->model == POST_DOMINATOR) {
@@ -642,7 +641,7 @@ void shader_core_stats::print(FILE *fout) const {
fprintf(fout, "gpgpu_n_param_mem_insn = %d\n", gpgpu_n_param_insn);
fprintf(fout, "gpgpu_n_shmem_bkconflict = %d\n", gpgpu_n_shmem_bkconflict);
- fprintf(fout, "gpgpu_n_cache_bkconflict = %d\n", gpgpu_n_cache_bkconflict);
+ fprintf(fout, "gpgpu_n_l1cache_bkconflict = %d\n", gpgpu_n_l1cache_bkconflict);
fprintf(fout, "gpgpu_n_intrawarp_mshr_merge = %d\n",
gpgpu_n_intrawarp_mshr_merge);
@@ -840,8 +839,8 @@ void shader_core_stats::visualizer_print(gzFile visualizer_file) {
gzprintf(visualizer_file, "\n");
// overall cache miss rates
- gzprintf(visualizer_file, "gpgpu_n_cache_bkconflict: %d\n",
- gpgpu_n_cache_bkconflict);
+ gzprintf(visualizer_file, "gpgpu_n_l1cache_bkconflict: %d\n",
+ gpgpu_n_l1cache_bkconflict);
gzprintf(visualizer_file, "gpgpu_n_shmem_bkconflict: %d\n",
gpgpu_n_shmem_bkconflict);
@@ -1046,6 +1045,25 @@ void shader_core_ctx::issue_warp(register_set &pipe_reg_set,
m_stats->shader_cycle_distro[2 + (*pipe_reg)->active_count()]++;
func_exec_inst(**pipe_reg);
+ // Add LDGSTS instructions into a buffer
+ unsigned int ldgdepbar_id = m_warp[warp_id]->m_ldgdepbar_id;
+ if (next_inst->m_is_ldgsts) {
+ if (m_warp[warp_id]->m_ldgdepbar_buf.size() == ldgdepbar_id + 1) {
+ m_warp[warp_id]->m_ldgdepbar_buf[ldgdepbar_id].push_back(*next_inst);
+ }
+ else {
+ assert(m_warp[warp_id]->m_ldgdepbar_buf.size() < ldgdepbar_id + 1);
+ std::vector<warp_inst_t> l;
+ l.push_back(*next_inst);
+ m_warp[warp_id]->m_ldgdepbar_buf.push_back(l);
+ }
+ // If the mask of the instruction is all 0, then the address is also 0,
+ // so that there's no need to check through the writeback
+ if (next_inst->get_active_mask() == 0) {
+ (m_warp[warp_id]->m_ldgdepbar_buf.back()).back().pc = -1;
+ }
+ }
+
if (next_inst->op == BARRIER_OP) {
m_warp[warp_id]->store_info_of_last_inst_at_barrier(*pipe_reg);
m_barriers.warp_reaches_barrier(m_warp[warp_id]->get_cta_id(), warp_id,
@@ -1053,6 +1071,37 @@ void shader_core_ctx::issue_warp(register_set &pipe_reg_set,
} else if (next_inst->op == MEMORY_BARRIER_OP) {
m_warp[warp_id]->set_membar();
+ } else if (next_inst->m_is_ldgdepbar) { // Add for LDGDEPBAR
+ m_warp[warp_id]->m_ldgdepbar_id++;
+ } else if (next_inst->m_is_depbar) { // Add for DEPBAR
+ // Set to true immediately when a DEPBAR instruction is met
+ m_warp[warp_id]->m_waiting_ldgsts = true;
+ m_warp[warp_id]->m_depbar_group = next_inst->m_depbar_group_no; // set in trace_driven.cc
+
+ // Record the last group that's possbily being monitored by this DEPBAR instr
+ m_warp[warp_id]->m_depbar_start_id = m_warp[warp_id]->m_ldgdepbar_id - 1;
+
+ // Record the last group that's actually being monitored by this DEPBAR instr
+ unsigned int end_group = m_warp[warp_id]->m_ldgdepbar_id - m_warp[warp_id]->m_depbar_group;
+
+ // Check for the case that the LDGSTSs monitored have finished when encountering the
+ // DEPBAR instruction
+ bool done_flag = true;
+ for (int i = 0; i < end_group; i++) {
+ for (int j = 0; j < m_warp[warp_id]->m_ldgdepbar_buf[i].size(); j++) {
+ if (m_warp[warp_id]->m_ldgdepbar_buf[i][j].pc != -1) {
+ done_flag = false;
+ goto UpdateDEPBAR;
+ }
+ }
+ }
+
+ UpdateDEPBAR:
+ if (done_flag) {
+ if (m_warp[warp_id]->m_waiting_ldgsts) {
+ m_warp[warp_id]->m_waiting_ldgsts = false;
+ }
+ }
}
updateSIMTStack(warp_id, *pipe_reg);
@@ -1796,12 +1845,50 @@ void ldst_unit::get_L1T_sub_stats(struct cache_sub_stats &css) const {
if (m_L1T) m_L1T->get_sub_stats(css);
}
+// Add this function to unset depbar
+void shader_core_ctx::unset_depbar(const warp_inst_t &inst) {
+ bool done_flag = true;
+ unsigned int end_group = m_warp[inst.warp_id()]->m_depbar_start_id == 0 ?
+ m_warp[inst.warp_id()]->m_ldgdepbar_buf.size() :
+ (m_warp[inst.warp_id()]->m_depbar_start_id - m_warp[inst.warp_id()]->m_depbar_group + 1);
+
+ if (inst.m_is_ldgsts) {
+ for (int i = 0; i < m_warp[inst.warp_id()]->m_ldgdepbar_buf.size(); i++) {
+ for (int j = 0; j < m_warp[inst.warp_id()]->m_ldgdepbar_buf[i].size(); j++) {
+ if (m_warp[inst.warp_id()]->m_ldgdepbar_buf[i][j].pc == inst.pc) {
+ // Handle the case that same pc results in multiple LDGSTS instructions
+ if (m_warp[inst.warp_id()]->m_ldgdepbar_buf[i][j].get_addr(0) == inst.get_addr(0)) {
+ m_warp[inst.warp_id()]->m_ldgdepbar_buf[i][j].pc = -1;
+ goto DoneWB;
+ }
+ }
+ }
+ }
+
+ DoneWB:
+ for (int i = 0; i < end_group; i++) {
+ for (int j = 0; j < m_warp[inst.warp_id()]->m_ldgdepbar_buf[i].size(); j++) {
+ if (m_warp[inst.warp_id()]->m_ldgdepbar_buf[i][j].pc != -1) {
+ done_flag = false;
+ goto UpdateDEPBAR;
+ }
+ }
+ }
+
+ UpdateDEPBAR:
+ if (done_flag) {
+ if (m_warp[inst.warp_id()]->m_waiting_ldgsts) {
+ m_warp[inst.warp_id()]->m_waiting_ldgsts = false;
+ }
+ }
+ }
+}
+
void shader_core_ctx::warp_inst_complete(const warp_inst_t &inst) {
#if 0
printf("[warp_inst_complete] uid=%u core=%u warp=%u pc=%#x @ time=%llu \n",
inst.get_uid(), m_sid, inst.warp_id(), inst.pc, m_gpu->gpu_tot_sim_cycle + m_gpu->gpu_sim_cycle);
#endif
-
if (inst.op_pipe == SP__OP)
m_stats->m_num_sp_committed[m_sid]++;
else if (inst.op_pipe == SFU__OP)
@@ -1880,6 +1967,7 @@ bool ldst_unit::shared_cycle(warp_inst_t &inst, mem_stage_stall_type &rc_fail,
if (stall) {
fail_type = S_MEM;
rc_fail = BK_CONF;
+ m_stats->gpgpu_n_shmem_bkconflict++;
} else
rc_fail = NO_RC_FAIL;
return !stall;
@@ -1906,6 +1994,14 @@ mem_stage_stall_type ldst_unit::process_cache_access(
if (inst.is_load()) {
for (unsigned r = 0; r < MAX_OUTPUT_VALUES; r++)
if (inst.out[r] > 0) m_pending_writes[inst.warp_id()][inst.out[r]]--;
+
+ // release LDGSTS
+ if (inst.m_is_ldgsts) {
+ m_pending_ldgsts[inst.warp_id()][inst.pc][inst.get_addr(0)]--;
+ if (m_pending_ldgsts[inst.warp_id()][inst.pc][inst.get_addr(0)] == 0) {
+ m_core->unset_depbar(inst);
+ }
+ }
}
if (!write_sent) delete mf;
} else if (status == RESERVATION_FAIL) {
@@ -1977,6 +2073,7 @@ mem_stage_stall_type ldst_unit::process_memory_access_queue_l1cache(
inst.accessq_pop_back();
} else {
result = BK_CONF;
+ m_stats->gpgpu_n_l1cache_bkconflict++;
delete mf;
break; // do not try again, just break from the loop and try the next
// cycle
@@ -2033,6 +2130,14 @@ void ldst_unit::L1_latency_queue_cycle() {
m_core->warp_inst_complete(mf_next->get_inst());
}
}
+
+ // release LDGSTS
+ if (mf_next->get_inst().m_is_ldgsts) {
+ m_pending_ldgsts[mf_next->get_inst().warp_id()][mf_next->get_inst().pc][mf_next->get_inst().get_addr(0)]--;
+ if (m_pending_ldgsts[mf_next->get_inst().warp_id()][mf_next->get_inst().pc][mf_next->get_inst().get_addr(0)] == 0) {
+ m_core->unset_depbar(mf_next->get_inst());
+ }
+ }
}
// For write hit in WB policy
@@ -2569,10 +2674,21 @@ void ldst_unit::writeback() {
insn_completed = true;
}
}
+ else if (m_next_wb.m_is_ldgsts) { // for LDGSTS instructions where no output register is used
+ m_pending_ldgsts[m_next_wb.warp_id()][m_next_wb.pc][m_next_wb.get_addr(0)]--;
+ if (m_pending_ldgsts[m_next_wb.warp_id()][m_next_wb.pc][m_next_wb.get_addr(0)] == 0) {
+ insn_completed = true;
+ }
+ break;
+ }
}
if (insn_completed) {
m_core->warp_inst_complete(m_next_wb);
+ if (m_next_wb.m_is_ldgsts) {
+ m_core->unset_depbar(m_next_wb);
+ }
}
+
m_next_wb.clear();
m_last_inst_gpu_sim_cycle = m_core->get_gpu()->gpu_sim_cycle;
m_last_inst_gpu_tot_sim_cycle = m_core->get_gpu()->gpu_tot_sim_cycle;
@@ -2794,6 +2910,14 @@ void ldst_unit::cycle() {
if (!pending_requests) {
m_core->warp_inst_complete(*m_dispatch_reg);
m_scoreboard->releaseRegisters(m_dispatch_reg);
+
+ // release LDGSTS
+ if (m_dispatch_reg->m_is_ldgsts) {
+ // m_pending_ldgsts[m_dispatch_reg->warp_id()][m_dispatch_reg->pc][m_dispatch_reg->get_addr(0)]--;
+ if (m_pending_ldgsts[m_dispatch_reg->warp_id()][m_dispatch_reg->pc][m_dispatch_reg->get_addr(0)] == 0) {
+ m_core->unset_depbar(*m_dispatch_reg);
+ }
+ }
}
m_core->dec_inst_in_pipeline(warp_id);
m_dispatch_reg->clear();
@@ -3928,6 +4052,8 @@ bool shd_warp_t::waiting() {
// the functional execution of the atomic when it hits DRAM can cause
// the wrong register to be read.
return true;
+ } else if (m_waiting_ldgsts) { // Waiting for LDGSTS to finish
+ return true;
}
return false;
}
@@ -4048,6 +4174,7 @@ int register_bank(int regnum, int wid, unsigned num_banks,
bool opndcoll_rfu_t::writeback(warp_inst_t &inst) {
assert(!inst.empty());
+
std::list<unsigned> regs = m_shader->get_regs_written(inst);
for (unsigned op = 0; op < MAX_REG_OPERANDS; op++) {
int reg_num = inst.arch_reg.dst[op]; // this math needs to match that used
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index fd4fc1f..0897302 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -123,6 +123,20 @@ class shd_warp_t {
// Jin: cdp support
m_cdp_latency = 0;
m_cdp_dummy = false;
+
+ // Ni: Initialize ldgdepbar_id
+ m_ldgdepbar_id = 0;
+ m_depbar_start_id = 0;
+ m_depbar_group = 0;
+
+ // Ni: Set waiting to false
+ m_waiting_ldgsts = false;
+
+ // Ni: Clear m_ldgdepbar_buf
+ for (int i = 0; i < m_ldgdepbar_buf.size(); i++) {
+ m_ldgdepbar_buf[i].clear();
+ }
+ m_ldgdepbar_buf.clear();
}
void init(address_type start_pc, unsigned cta_id, unsigned wid,
const std::bitset<MAX_WARP_SIZE> &active,
@@ -140,6 +154,20 @@ class shd_warp_t {
// Jin: cdp support
m_cdp_latency = 0;
m_cdp_dummy = false;
+
+ // Ni: Initialize ldgdepbar_id
+ m_ldgdepbar_id = 0;
+ m_depbar_start_id = 0;
+ m_depbar_group = 0;
+
+ // Ni: Set waiting to false
+ m_waiting_ldgsts = false;
+
+ // Ni: Clear m_ldgdepbar_buf
+ for (int i = 0; i < m_ldgdepbar_buf.size(); i++) {
+ m_ldgdepbar_buf[i].clear();
+ }
+ m_ldgdepbar_buf.clear();
}
bool functional_done() const;
@@ -288,6 +316,14 @@ class shd_warp_t {
public:
unsigned int m_cdp_latency;
bool m_cdp_dummy;
+
+ // Ni: LDGDEPBAR barrier support
+ public:
+ unsigned int m_ldgdepbar_id; // LDGDEPBAR barrier ID
+ std::vector<std::vector<warp_inst_t>> m_ldgdepbar_buf; // LDGDEPBAR barrier buffer
+ unsigned int m_depbar_start_id;
+ unsigned int m_depbar_group;
+ bool m_waiting_ldgsts; // Ni: Whether the warp is waiting for the LDGSTS instrs to finish
};
inline unsigned hw_tid_from_wid(unsigned wid, unsigned warp_size, unsigned i) {
@@ -351,8 +387,8 @@ class scheduler_unit { // this can be copied freely, so can be used in std
m_sfu_out(sfu_out),
m_int_out(int_out),
m_tensor_core_out(tensor_core_out),
- m_spec_cores_out(spec_cores_out),
m_mem_out(mem_out),
+ m_spec_cores_out(spec_cores_out),
m_id(id) {}
virtual ~scheduler_unit() {}
virtual void add_supervised_warp_id(int i) {
@@ -1314,6 +1350,15 @@ class ldst_unit : public pipelined_simd_unit {
const memory_config *mem_config, class shader_core_stats *stats,
unsigned sid, unsigned tpc);
+ // Add a structure to record the LDGSTS instructions,
+ // similar to m_pending_writes, but since LDGSTS does not have a output register
+ // to write to, so a new structure needs to be added
+ /* A multi-level map: unsigned (warp_id) -> unsigned (pc) -> unsigned (addr) -> unsigned (count)
+ */
+ std::map<unsigned /*warp_id*/,
+ std::map<unsigned /*pc*/,
+ std::map<unsigned /*addr*/, unsigned /*count*/>>>
+ m_pending_ldgsts;
// modifiers
virtual void issue(register_set &inst);
bool is_issue_partitioned() { return false; }
@@ -1735,7 +1780,7 @@ struct shader_core_stats_pod {
unsigned gpgpu_n_const_insn;
unsigned gpgpu_n_param_insn;
unsigned gpgpu_n_shmem_bkconflict;
- unsigned gpgpu_n_cache_bkconflict;
+ unsigned gpgpu_n_l1cache_bkconflict;
int gpgpu_n_intrawarp_mshr_merge;
unsigned gpgpu_n_cmem_portconflict;
unsigned gpu_stall_shd_mem_breakdown[N_MEM_STAGE_ACCESS_TYPE]
@@ -2069,6 +2114,9 @@ class shader_core_ctx : public core_t {
// modifiers
virtual void warp_exit(unsigned warp_id);
+ // Ni: Unset ldgdepbar
+ void unset_depbar(const warp_inst_t &inst);
+
// accessors
virtual bool warp_waiting_at_barrier(unsigned warp_id) const;
void get_pdom_stack_top_info(unsigned tid, unsigned *pc, unsigned *rpc) const;
diff --git a/src/gpgpu-sim/shader_trace.h b/src/gpgpu-sim/shader_trace.h
index e7486d8..367262c 100644
--- a/src/gpgpu-sim/shader_trace.h
+++ b/src/gpgpu-sim/shader_trace.h
@@ -38,7 +38,7 @@
#define SCHED_PRINT_STR SHADER_PRINT_STR "Scheduler %d - "
#define SHADER_DTRACE(x) \
(DTRACE(x) && \
- (Trace::sampling_core == get_sid() || Trace::sampling_core == -1))
+ (Trace::sampling_core == (int)get_sid() || Trace::sampling_core == -1))
// Intended to be called from inside components of a shader core.
// Depends on a get_sid() function
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 02:28:34 +0000