5 files changed, 46 insertions, 6 deletions

diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc
index 745bec4..35b1d55 100644
--- a/src/gpgpu-sim/dram.cc
+++ b/src/gpgpu-sim/dram.cc
@@ -168,6 +168,8 @@ dram_req_t::dram_req_t( class mem_fetch *mf )
 
 void dram_t::push( class mem_fetch *data ) 
 {
+   assert(id == data->get_tlx_addr().chip); // Ensure request is in correct memory partition
+
    dram_req_t *mrq = new dram_req_t(data);
    data->set_status(IN_PARTITION_MC_INTERFACE_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
    mrqq->push(mrq);
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index 3f44eea..a09c92e 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -29,6 +29,22 @@
 #include "stat-tool.h"
 #include <assert.h>
 
+
+void l2_cache_config::init(linear_to_raw_address_translation *address_mapping){
+	cache_config::init();
+	m_address_mapping = address_mapping;
+}
+
+unsigned l2_cache_config::set_index(new_addr_type addr) const{
+	if(!m_address_mapping){
+		return(addr >> m_line_sz_log2) & (m_nset-1);
+	}else{
+		// Calculate set index without memory partition bits to reduce set camping
+		new_addr_type part_addr = m_address_mapping->partition_address(addr);
+		return(part_addr >> m_line_sz_log2) & (m_nset -1);
+	}
+}
+
 tag_array::~tag_array() 
 {
     delete m_lines;
@@ -582,6 +598,7 @@ enum cache_request_status read_only_cache::access( new_addr_type addr, mem_fetch
 /// It is write-evict (global) or write-back (local) at the granularity of individual blocks (Set by GPGPU-Sim configuration file)
 /// (the policy used in fermi according to the CUDA manual)
 enum cache_request_status l1_cache::access( new_addr_type addr, mem_fetch *mf, unsigned time, std::list<cache_event> &events ){
+
 	assert( mf->get_data_size() <= m_config.get_line_sz());
 	bool wr = mf->get_is_write();
 	new_addr_type block_addr = m_config.block_addr(addr);
@@ -609,6 +626,7 @@ enum cache_request_status l1_cache::access( new_addr_type addr, mem_fetch *mf, u
 /// Models second level shared cache with global write-back and write-allocate policies
 /// Currently the same as l1_cache, but separated to allow for different implementations
 enum cache_request_status l2_cache::access( new_addr_type addr, mem_fetch *mf, unsigned time, std::list<cache_event> &events ){
+
 	assert( mf->get_data_size() <= m_config.get_line_sz());
 	bool wr = mf->get_is_write();
 	new_addr_type block_addr = m_config.block_addr(addr);
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index ac5fee8..2d50e67 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -35,6 +35,8 @@
 #include "../abstract_hardware_model.h"
 #include "../tr1_hash_map.h"
 
+#include "addrdec.h"
+
 enum cache_block_state {
     INVALID,
     RESERVED,
@@ -118,6 +120,7 @@ enum mshr_config_t {
     ASSOC // normal cache 
 };
 
+
 class cache_config {
 public:
     cache_config() 
@@ -175,6 +178,7 @@ public:
         case 'N': m_write_alloc_policy = NO_WRITE_ALLOCATE; break;
         default: exit_parse_error();
         }
+
     }
     bool disabled() const { return m_disabled;}
     unsigned get_line_sz() const
@@ -195,13 +199,19 @@ public:
                  m_nset, m_assoc, m_line_sz );
     }
 
-    unsigned set_index( new_addr_type addr ) const 
+    virtual unsigned set_index( new_addr_type addr ) const
     {
         return(addr >> m_line_sz_log2) & (m_nset-1);
     }
+
     new_addr_type tag( new_addr_type addr ) const
     {
-        return addr >> (m_line_sz_log2+m_nset_log2);
+    	// For generality, the tag includes both index and tag. This allows for more complex set index
+    	// calculations that can result in different indexes mapping to the same set, thus the full
+    	// tag + index is required to check for hit/miss. Tag is now identical to the block address.
+
+        //return addr >> (m_line_sz_log2+m_nset_log2);
+    	return addr & ~(m_line_sz-1);
     }
     new_addr_type block_addr( new_addr_type addr ) const
     {
@@ -210,7 +220,7 @@ public:
 
     char *m_config_string;
 
-private:
+protected:
     void exit_parse_error()
     {
         printf("GPGPU-Sim uArch: cache configuration parsing error (%s)\n", m_config_string );
@@ -256,6 +266,16 @@ private:
 };
 
 
+class l2_cache_config : public cache_config {
+public:
+	l2_cache_config() : cache_config(){}
+	void init(linear_to_raw_address_translation *address_mapping);
+	virtual unsigned set_index(new_addr_type addr) const;
+
+private:
+	linear_to_raw_address_translation *m_address_mapping;
+};
+
 class tag_array {
 public:
     tag_array( const cache_config &config, int core_id, int type_id );
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index c04c1c1..6e5c3f0 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -202,14 +202,14 @@ struct memory_config {
       tWTP = (WL+(BL/data_command_freq_ratio)+tWR);
       dram_atom_size = BL * busW * gpu_n_mem_per_ctrlr; // burst length x bus width x # chips per partition 
       m_address_mapping.init(m_n_mem);
-      m_L2_config.init();
+      m_L2_config.init(&m_address_mapping);
       m_valid = true;
       icnt_flit_size = 32; // Default 32
    }
    void reg_options(class OptionParser * opp);
 
    bool m_valid;
-   cache_config m_L2_config;
+   l2_cache_config m_L2_config;
    bool m_L2_texure_only;
 
    char *gpgpu_dram_timing_opt;
diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc
index 56b145c..21f837d 100644
--- a/src/gpgpu-sim/l2cache.cc
+++ b/src/gpgpu-sim/l2cache.cc
@@ -145,7 +145,7 @@ void memory_partition_unit::cache_cycle( unsigned cycle )
             // L2 is enabled and access is for L2
             if ( !m_L2_icnt_queue->full() ) {
                 std::list<cache_event> events;
-                enum cache_request_status status = m_L2cache->access(mf->get_partition_addr(),mf,gpu_sim_cycle+gpu_tot_sim_cycle,events);
+                enum cache_request_status status = m_L2cache->access(mf->get_addr(),mf,gpu_sim_cycle+gpu_tot_sim_cycle,events);
                 bool write_sent = was_write_sent(events);
                 bool read_sent = was_read_sent(events);