diff options
Diffstat (limited to 'src/gpgpu-sim')
| -rw-r--r-- | src/gpgpu-sim/dram_sched.cc | 2 | ||||
| -rw-r--r-- | src/gpgpu-sim/l2cache.h | 1 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 9 |
3 files changed, 11 insertions, 1 deletions
diff --git a/src/gpgpu-sim/dram_sched.cc b/src/gpgpu-sim/dram_sched.cc index 48e96ee..e556edc 100644 --- a/src/gpgpu-sim/dram_sched.cc +++ b/src/gpgpu-sim/dram_sched.cc @@ -78,6 +78,7 @@ void frfcfs_scheduler::data_collection(unsigned int bank) dram_req_t *frfcfs_scheduler::schedule( unsigned bank, unsigned curr_row ) { + int row_hit = 0; if ( m_last_row[bank] == NULL ) { if ( m_queue[bank].empty() ) return NULL; @@ -94,6 +95,7 @@ dram_req_t *frfcfs_scheduler::schedule( unsigned bank, unsigned curr_row ) } } + row_hit=1; std::list<dram_req_t*>::iterator next = m_last_row[bank]->back(); dram_req_t *req = (*next); diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h index 15c3806..22640b8 100644 --- a/src/gpgpu-sim/l2cache.h +++ b/src/gpgpu-sim/l2cache.h @@ -121,7 +121,6 @@ private: class L2interface : public mem_fetch_interface { public: L2interface( memory_partition_unit *unit ) { m_unit=unit; } - virtual ~L2interface(){} virtual bool full( unsigned size, bool write) const { // assume read and write packets all same size diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index a7daeaa..ddb544a 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -672,6 +672,10 @@ void TwoLevelScheduler::cycle() { //Do the scheduling only from activeWarps //If you schedule an instruction, move it to the end of the list + bool valid_inst = false; // there was one warp with a valid instruction to issue (didn't require flush due to control hazard) + bool ready_inst = false; // of the valid instructions, there was one not waiting for pending register writes + bool issued_inst = false; // of these we issued one + for ( std::list<int>::iterator warp_id = activeWarps.begin(); warp_id != activeWarps.end(); warp_id++) { @@ -691,13 +695,16 @@ void TwoLevelScheduler::cycle() { warp(*warp_id).set_next_pc(pc); warp(*warp_id).ibuffer_flush(); } else { + valid_inst = true; if ( !m_scoreboard->checkCollision(*warp_id, pI) ) { + ready_inst = true; const active_mask_t &active_mask = m_simt_stack[*warp_id]->get_active_mask(); assert( warp(*warp_id).inst_in_pipeline() ); if ( (pI->op == LOAD_OP) || (pI->op == STORE_OP) || (pI->op == MEMORY_BARRIER_OP) ) { if( m_mem_out->has_free() ) { m_shader->issue_warp(*m_mem_out,pI,active_mask,*warp_id); issued++; + issued_inst=true; warp_inst_issued = true; // Move it to pendingWarps unsigned currwarp = *warp_id; @@ -711,6 +718,7 @@ void TwoLevelScheduler::cycle() { // always prefer SP pipe for operations that can use both SP and SFU pipelines m_shader->issue_warp(*m_sp_out,pI,active_mask,*warp_id); issued++; + issued_inst=true; warp_inst_issued = true; //Move it to end of the activeWarps unsigned currwarp = *warp_id; @@ -720,6 +728,7 @@ void TwoLevelScheduler::cycle() { if( sfu_pipe_avail ) { m_shader->issue_warp(*m_sfu_out,pI,active_mask,*warp_id); issued++; + issued_inst=true; warp_inst_issued = true; //Move it to end of the activeWarps unsigned currwarp = *warp_id; |