diff options
Diffstat (limited to 'src/gpgpu-sim')
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.cc | 6 | ||||
| -rw-r--r-- | src/gpgpu-sim/mem_fetch.cc | 42 | ||||
| -rw-r--r-- | src/gpgpu-sim/mem_fetch.h | 59 | ||||
| -rw-r--r-- | src/gpgpu-sim/mem_latency_stat.cc | 2 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 213 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.h | 5 | ||||
| -rw-r--r-- | src/gpgpu-sim/visualizer.cc | 4 |
7 files changed, 116 insertions, 215 deletions
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index e3e54dc..a7b2ecf 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -259,8 +259,8 @@ void gpgpu_sim::reg_options(option_parser_t opp) "Size of shared memory per shader core (default 16kB)", "16384"); - option_parser_register(opp, "-gpgpu_shmem_pipe_speedup", OPT_INT32, &m_shader_config->gpgpu_shmem_pipe_speedup, - "Number of groups each warp is divided for shared memory bank conflict check", + option_parser_register(opp, "-gpgpu_shmem_warp_parts", OPT_INT32, &m_shader_config->shmem_warp_parts, + "Number of portions a warp is divided into for shared memory bank conflict check ", "2"); option_parser_register(opp, "-gpgpu_deadlock_detect", OPT_BOOL, &gpu_deadlock_detect, @@ -431,7 +431,7 @@ void gpgpu_sim::init_gpu() sscanf(gpgpu_runtime_stat, "%d:%x", &gpu_stat_sample_freq, &gpu_runtime_stat_flag); m_shader_config->pdom_sched_type = m_pdom_sched_type; - m_shader_config->gpgpu_n_shmem_bank=16; + m_shader_config->num_shmem_bank=16; m_cluster = new simt_core_cluster*[m_shader_config->n_simt_clusters]; for (unsigned i=0;i<m_shader_config->n_simt_clusters;i++) diff --git a/src/gpgpu-sim/mem_fetch.cc b/src/gpgpu-sim/mem_fetch.cc index 74a1ac1..aa0006c 100644 --- a/src/gpgpu-sim/mem_fetch.cc +++ b/src/gpgpu-sim/mem_fetch.cc @@ -71,36 +71,30 @@ unsigned mem_fetch::sm_next_mf_request_uid=1; -mem_fetch::mem_fetch( new_addr_type addr, - unsigned data_size, - unsigned ctrl_size, - unsigned sid, - unsigned tpc, +mem_fetch::mem_fetch( const mem_access_t &access, + const warp_inst_t *inst, + unsigned ctrl_size, unsigned wid, - warp_inst_t *inst, - bool write, - partial_write_mask_t partial_write_mask, - enum mem_access_type mem_acc, - enum mf_type type, - const memory_config *config ) : m_inst() + unsigned sid, + unsigned tpc, + const class memory_config *config ) { m_request_uid = sm_next_mf_request_uid++; - - m_addr = addr; - m_data_size = data_size; + m_access = access; + if( inst ) { + m_inst = *inst; + assert( wid == m_inst.warp_id() ); + } + m_data_size = access.get_size(); m_ctrl_size = ctrl_size; m_sid = sid; - m_wid = wid; m_tpc = tpc; - if( inst ) m_inst = *inst; - m_write = write; - config->m_address_mapping.addrdec_tlx(addr,&m_raw_addr); - m_partition_addr = config->m_address_mapping.partition_address(addr); - m_mem_acc = mem_acc; - m_type = type; + m_wid = wid; + config->m_address_mapping.addrdec_tlx(access.get_addr(),&m_raw_addr); + m_partition_addr = config->m_address_mapping.partition_address(access.get_addr()); + m_type = m_access.is_write()?WR_REQ:RD_REQ; m_timestamp = gpu_sim_cycle + gpu_tot_sim_cycle; m_timestamp2 = 0; - m_status = MEM_FETCH_INITIALIZED; m_status_change = gpu_sim_cycle + gpu_tot_sim_cycle; } @@ -137,8 +131,8 @@ void mem_fetch::print( FILE *fp, bool print_inst ) const fprintf(fp," <NULL mem_fetch pointer>\n"); return; } - fprintf(fp," mf: uid=%6u, addr=0x%08llx, sid=%2u, wid=%2u, %s, partition=%u, ", - m_request_uid, m_addr, m_sid, m_wid, (m_write?"write":"read "), m_raw_addr.chip); + fprintf(fp," mf: uid=%6u, sid=%2u, partition=%u, ", m_request_uid, m_sid, m_raw_addr.chip ); + m_access.print(fp); if( (unsigned)m_status < NUM_MEM_REQ_STAT ) fprintf(fp," status = %s (%llu), ", Status_str[m_status], m_status_change ); else diff --git a/src/gpgpu-sim/mem_fetch.h b/src/gpgpu-sim/mem_fetch.h index 8fe09e0..05e2206 100644 --- a/src/gpgpu-sim/mem_fetch.h +++ b/src/gpgpu-sim/mem_fetch.h @@ -73,22 +73,8 @@ enum mf_type { RD_REQ = 0, - WT_REQ, - REPLY_DATA, // send to shader - L2_WTBK_DATA, - N_MF_TYPE -}; - -enum mem_access_type { - GLOBAL_ACC_R = 0, - LOCAL_ACC_R = 1, - CONST_ACC_R = 2, - TEXTURE_ACC_R = 3, - GLOBAL_ACC_W = 4, - LOCAL_ACC_W = 5, - L2_WRBK_ACC = 6, - INST_ACC_R = 7, - NUM_MEM_ACCESS_TYPE = 8 + WR_REQ, + REPLY_DATA // send to shader }; enum mem_fetch_status { @@ -113,23 +99,15 @@ enum mem_fetch_status { NUM_MEM_REQ_STAT }; -const unsigned partial_write_mask_bits = 128; //must be at least size of largest memory access. -typedef std::bitset<partial_write_mask_bits> partial_write_mask_t; - class mem_fetch { public: - mem_fetch( new_addr_type addr, - unsigned data_size, - unsigned ctrl_size, - unsigned sid, - unsigned tpc, - unsigned wid, - warp_inst_t *inst, - bool write, - partial_write_mask_t partial_write_mask, - enum mem_access_type mem_acc, - enum mf_type type, - const class memory_config *config ); + mem_fetch( const mem_access_t &access, + const warp_inst_t *inst, + unsigned ctrl_size, + unsigned wid, + unsigned sid, + unsigned tpc, + const class memory_config *config ); ~mem_fetch(); void set_status( enum mem_fetch_status status, unsigned long long cycle ); @@ -143,9 +121,9 @@ public: void set_data_size( unsigned size ) { m_data_size=size; } unsigned get_ctrl_size() const { return m_ctrl_size; } unsigned size() const { return m_data_size+m_ctrl_size; } - new_addr_type get_addr() const { return m_addr; } + new_addr_type get_addr() const { return m_access.get_addr(); } new_addr_type get_partition_addr() const { return m_partition_addr; } - bool get_is_write() const { return m_write; } + bool get_is_write() const { return m_access.is_write(); } unsigned get_request_uid() const { return m_request_uid; } unsigned get_sid() const { return m_sid; } unsigned get_tpc() const { return m_tpc; } @@ -154,12 +132,14 @@ public: bool isconst() const; enum mf_type get_type() const { return m_type; } bool isatomic() const; + void set_return_timestamp( unsigned t ) { m_timestamp2=t; } void set_icnt_receive_time( unsigned t ) { m_icnt_receive_time=t; } unsigned get_timestamp() const { return m_timestamp; } unsigned get_return_timestamp() const { return m_timestamp2; } unsigned get_icnt_receive_time() const { return m_icnt_receive_time; } - enum mem_access_type get_mem_acc() const { return m_mem_acc; } + + enum mem_access_type get_access_type() const { return m_access.get_type(); } address_type get_pc() const { return m_inst.empty()?-1:m_inst.pc; } const warp_inst_t &get_inst() { return m_inst; } enum mem_fetch_status get_status() const { return m_status; } @@ -176,15 +156,12 @@ private: unsigned long long m_status_change; // request type, address, size, mask - bool m_write; - enum mem_access_type m_mem_acc; - enum mf_type m_type; - new_addr_type m_addr; // linear (physical) address - new_addr_type m_partition_addr; // linear physical address *within* dram partition (partition bank select bits squeezed out) - addrdec_t m_raw_addr; // raw physical address (i.e., decoded DRAM chip-row-bank-column address) - partial_write_mask_t m_write_mask; + mem_access_t m_access; unsigned m_data_size; // how much data is being written unsigned m_ctrl_size; // how big would all this meta data be in hardware (does not necessarily match actual size of mem_fetch) + new_addr_type m_partition_addr; // linear physical address *within* dram partition (partition bank select bits squeezed out) + addrdec_t m_raw_addr; // raw physical address (i.e., decoded DRAM chip-row-bank-column address) + enum mf_type m_type; // statistics unsigned m_timestamp; // set to gpu_sim_cycle+gpu_tot_sim_cycle at struct creation diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc index f78717e..5b4d3ac 100644 --- a/src/gpgpu-sim/mem_latency_stat.cc +++ b/src/gpgpu-sim/mem_latency_stat.cc @@ -229,7 +229,7 @@ void memory_stats_t::memlatstat_dram_access(mem_fetch *mf) } if (mf->get_pc() != (unsigned)-1) ptx_file_line_stats_add_dram_traffic(mf->get_pc(),1); - mem_access_type_stats[mf->get_mem_acc()][dram_id][bank]++; + mem_access_type_stats[mf->get_access_type()][dram_id][bank]++; } } diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 0604bb8..5c73126 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -425,17 +425,13 @@ void shader_core_ctx::fetch() unsigned offset_in_block = pc & (m_config->m_L1I_config.get_line_sz()-1); if( (offset_in_block+nbytes) > m_config->m_L1I_config.get_line_sz() ) nbytes = (m_config->m_L1I_config.get_line_sz()-offset_in_block); - mem_fetch *mf = new mem_fetch(ppc, - nbytes, + mem_access_t acc(INST_ACC_R,ppc,nbytes,false); + mem_fetch *mf = new mem_fetch(acc, + NULL/*we don't have an instruction yet*/, READ_PACKET_SIZE, + warp_id, m_sid, m_tpc, - warp_id, - NULL/*we don't have an instruction yet*/, - false, - NO_PARTIAL_WRITE, - INST_ACC_R, - RD_REQ, m_memory_config ); enum cache_request_status status = m_L1I->access( (new_addr_type)ppc, mf, gpu_sim_cycle+gpu_tot_sim_cycle ); if( status == MISS ) { @@ -481,6 +477,8 @@ void shader_core_ctx::func_exec_inst( warp_inst_t &inst ) } } } + if( inst.is_load() || inst.is_store() ) + inst.generate_mem_accesses(); } void shader_core_ctx::issue_warp( warp_inst_t *&pipe_reg, const warp_inst_t *next_inst, unsigned active_mask, unsigned warp_id ) @@ -609,51 +607,16 @@ void shader_core_ctx::execute() } } -mem_fetch *ldst_unit::create_data_mem_fetch(warp_inst_t &inst, mem_access_t &access) +mem_fetch *ldst_unit::create_data_mem_fetch(const warp_inst_t &inst, const mem_access_t &access) { - bool is_write = inst.is_store(); - mem_access_type access_type; - switch (inst.space.get_type()) { - case const_space: - case param_space_kernel: - access_type = CONST_ACC_R; - break; - case tex_space: - access_type = TEXTURE_ACC_R; - break; - case global_space: - access_type = is_write? GLOBAL_ACC_W: GLOBAL_ACC_R; - break; - case local_space: - case param_space_local: - access_type = is_write? LOCAL_ACC_W: LOCAL_ACC_R; - break; - default: assert(0); break; - } - unsigned request_size = access.req_size; - partial_write_mask_t write_mask = NO_PARTIAL_WRITE; - if (is_write) { - for (unsigned i=0;i < access.warp_indices.size();i++) { - unsigned w = access.warp_indices[i]; - int data_offset = inst.get_addr(w) & ((unsigned long long int)access.req_size - 1); - for (unsigned b = data_offset; b < data_offset + inst.data_size; b++) - write_mask.set(b); - } - } warp_inst_t inst_copy = inst; - inst_copy.set_active(access.warp_indices); - unsigned warp_id = inst.warp_id(); - mem_fetch *mf = new mem_fetch(access.addr, - request_size, - is_write?WRITE_PACKET_SIZE:READ_PACKET_SIZE, - m_sid, - m_tpc, - warp_id, - &inst_copy, - is_write, - write_mask, - access_type, - is_write?WT_REQ:RD_REQ, + inst_copy.set_active(access.get_warp_mask()); + mem_fetch *mf = new mem_fetch(access, + &inst_copy, + access.is_write()?WRITE_PACKET_SIZE:READ_PACKET_SIZE, + inst.warp_id(), + m_sid, + m_tpc, m_memory_config); return mf; } @@ -675,59 +638,51 @@ void shader_core_ctx::writeback() bool ldst_unit::shared_cycle( warp_inst_t &inst, mem_stage_stall_type &rc_fail, mem_stage_access_type &fail_type) { - // Process a single cycle of activity from the shared memory queue. if( inst.space.get_type() != shared_space ) return true; - - //consume port number orders from the top of the queue; - for( int i = 0; i < m_config->gpgpu_shmem_port_per_bank; i++ ) { - if (inst.accessq_empty()) - break; - unsigned current_order = inst.accessq_back().order; - //consume all requests of the same order (concurrent bank requests) - while ((!inst.accessq_empty()) && inst.accessq_back().order == current_order) - inst.accessq_pop_back(); - } - if( !inst.accessq_empty() ) { - rc_fail = BK_CONF; - fail_type = S_MEM; - m_stats->gpgpu_n_shmem_bkconflict++; - } - return inst.accessq_empty(); //done if empty. + bool stall = inst.dispatch_delay(); + if( stall ) { + fail_type = S_MEM; + rc_fail = BK_CONF; + } else + rc_fail = NO_RC_FAIL; + return !stall; } mem_stage_stall_type ldst_unit::process_memory_access_queue( cache_t *cache, warp_inst_t &inst ) { mem_stage_stall_type result = NO_RC_FAIL; - unsigned current_order = inst.accessq_back().order; - while ((!inst.accessq_empty()) && inst.accessq_back().order == current_order) { - mem_fetch *mf = create_data_mem_fetch(inst,inst.accessq_back()); - enum cache_request_status status = cache->access(mf->get_addr(),mf,gpu_sim_cycle+gpu_tot_sim_cycle); - if( status == HIT ) { - inst.accessq_pop_back(); - delete mf; - } else if( status == RESERVATION_FAIL ) { - result = COAL_STALL; // todo: unify enums - delete mf; - break; - } else { - assert( status == MISS || status == HIT_RESERVED ); - inst.accessq_pop_back(); - if( inst.is_load() ) { - for( unsigned r=0; r < 4; r++) - if(inst.out[r] > 0) - m_pending_writes[inst.warp_id()][inst.out[r]]++; - } - } + if( inst.accessq_empty() ) + return result; + + const mem_access_t &access = inst.accessq_back(); + mem_fetch *mf = create_data_mem_fetch(inst,inst.accessq_back()); + enum cache_request_status status = cache->access(mf->get_addr(),mf,gpu_sim_cycle+gpu_tot_sim_cycle); + + if ( status == HIT ) { + inst.accessq_pop_back(); + delete mf; + } else if ( status == RESERVATION_FAIL ) { + result = COAL_STALL; + delete mf; + } else { + inst.clear_active( access.get_warp_mask() ); // threads in mf writeback when mf returns + assert( status == MISS || status == HIT_RESERVED ); + inst.accessq_pop_back(); + if ( inst.is_load() ) { + for ( unsigned r=0; r < 4; r++) + if (inst.out[r] > 0) + m_pending_writes[inst.warp_id()][inst.out[r]]++; + } } - if( !inst.accessq_empty() && (inst.accessq_back().order != current_order) ) - result = BK_CONF; + if( !inst.accessq_empty() ) + result = BK_CONF; return result; } bool ldst_unit::constant_cycle( warp_inst_t &inst, mem_stage_stall_type &rc_fail, mem_stage_access_type &fail_type) { - if( (inst.space.get_type() != const_space) && (inst.space.get_type() != param_space_kernel) ) + if( inst.empty() || ((inst.space.get_type() != const_space) && (inst.space.get_type() != param_space_kernel)) ) return true; mem_stage_stall_type fail = process_memory_access_queue(m_L1C,inst); if (fail != NO_RC_FAIL){ @@ -742,7 +697,7 @@ bool ldst_unit::constant_cycle( warp_inst_t &inst, mem_stage_stall_type &rc_fail bool ldst_unit::texture_cycle( warp_inst_t &inst, mem_stage_stall_type &rc_fail, mem_stage_access_type &fail_type) { - if( inst.space.get_type() != tex_space ) + if( inst.empty() || inst.space.get_type() != tex_space ) return true; mem_stage_stall_type fail = process_memory_access_queue(m_L1T,inst); if (fail != NO_RC_FAIL){ @@ -754,27 +709,28 @@ bool ldst_unit::texture_cycle( warp_inst_t &inst, mem_stage_stall_type &rc_fail, bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_reason, mem_stage_access_type &access_type ) { - if( (inst.space.get_type() != global_space) && - (inst.space.get_type() != local_space) && - (inst.space.get_type() != param_space_local) ) + if( inst.empty() || + ((inst.space.get_type() != global_space) && + (inst.space.get_type() != local_space) && + (inst.space.get_type() != param_space_local)) ) return true; + assert( !inst.accessq_empty() ); mem_stage_stall_type stall_cond = NO_RC_FAIL; - unsigned current_order = inst.accessq_back().order; - while ((!inst.accessq_empty()) && inst.accessq_back().order == current_order) { - if( m_icnt->full(inst.accessq_back().req_size, inst.is_store()) ) { - stall_cond = ICNT_RC_FAIL; - break; - } else { - mem_fetch *mf = create_data_mem_fetch(inst,inst.accessq_back()); - m_icnt->push(mf); - inst.accessq_pop_back(); - if( inst.is_load() ) { - for( unsigned r=0; r < 4; r++) - if(inst.out[r] > 0) - m_pending_writes[inst.warp_id()][inst.out[r]]++; - } else if( inst.is_store() ) - m_core->inc_store_req( inst.warp_id() ); - } + const mem_access_t &access = inst.accessq_back(); + unsigned size = access.get_size(); + if( m_icnt->full(size, inst.is_store()) ) { + stall_cond = ICNT_RC_FAIL; + } else { + mem_fetch *mf = create_data_mem_fetch(inst,access); + m_icnt->push(mf); + inst.accessq_pop_back(); + inst.clear_active( access.get_warp_mask() ); + if( inst.is_load() ) { + for( unsigned r=0; r < 4; r++) + if(inst.out[r] > 0) + m_pending_writes[inst.warp_id()][inst.out[r]]++; + } else if( inst.is_store() ) + m_core->inc_store_req( inst.warp_id() ); } if( !inst.accessq_empty() ) stall_cond = COAL_STALL; @@ -785,12 +741,11 @@ bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_rea access_type = (iswrite)?L_MEM_ST:L_MEM_LD; else access_type = (iswrite)?G_MEM_ST:G_MEM_LD; - if (stall_cond == BK_CONF || stall_cond == COAL_STALL) - m_stats->gpgpu_n_cache_bkconflict++; } - return inst.accessq_empty(); //done if empty. + return inst.accessq_empty(); } + bool ldst_unit::response_buffer_full() const { return m_response_fifo.size() >= m_config->ldst_unit_response_queue_size; @@ -807,20 +762,6 @@ void ldst_unit::flush() // no L1D } -void ldst_unit::generate_mem_accesses(warp_inst_t &inst) -{ - // Called once per warp when warp enters ld/st unit. - // Generates a list of memory accesses, but does not perform the memory access. - if( inst.empty() ) - return; - if( inst.op == MEMORY_BARRIER_OP ) - return; - if( inst.mem_accesses_created() ) - return; - inst.get_memory_access_list(); - inst.set_mem_accesses_created(); -} - simd_function_unit::simd_function_unit( const shader_core_config *config ) { m_config=config; @@ -975,10 +916,7 @@ void ldst_unit::cycle() m_L1T->cycle(); m_L1C->cycle(); - // process new memory requests warp_inst_t &pipe_reg = *m_dispatch_reg; - generate_mem_accesses(pipe_reg); - enum mem_stage_stall_type rc_fail = NO_RC_FAIL; mem_stage_access_type type; bool done = true; @@ -1975,7 +1913,7 @@ void simt_core_cluster::icnt_inject_request_packet(class mem_fetch *mf) // stats if (mf->get_is_write()) m_stats->made_write_mfs++; else m_stats->made_read_mfs++; - switch (mf->get_mem_acc()) { + switch (mf->get_access_type()) { case CONST_ACC_R: m_stats->gpgpu_n_mem_const++; break; case TEXTURE_ACC_R: m_stats->gpgpu_n_mem_texture++; break; case GLOBAL_ACC_R: m_stats->gpgpu_n_mem_read_global++; break; @@ -1985,17 +1923,12 @@ void simt_core_cluster::icnt_inject_request_packet(class mem_fetch *mf) case INST_ACC_R: m_stats->gpgpu_n_mem_read_inst++; break; default: assert(0); } - unsigned destination = mf->get_tlx_addr().chip; mf->set_status(IN_ICNT_TO_MEM,gpu_sim_cycle+gpu_tot_sim_cycle); - if (!mf->get_is_write()) { - mf->set_type(RD_REQ); + if (!mf->get_is_write()) ::icnt_push(m_cluster_id, m_config->mem2device(destination), (void*)mf, mf->get_ctrl_size() ); - } else { - mf->set_type(WT_REQ); + else ::icnt_push(m_cluster_id, m_config->mem2device(destination), (void*)mf, mf->size()); - //gpgpu_n_sent_writes++; - } } void simt_core_cluster::icnt_cycle() @@ -2003,7 +1936,7 @@ void simt_core_cluster::icnt_cycle() if( !m_response_fifo.empty() ) { mem_fetch *mf = m_response_fifo.front(); unsigned cid = sid_to_cid(mf->get_sid()); - if( mf->get_mem_acc() == INST_ACC_R ) { + if( mf->get_access_type() == INST_ACC_R ) { // instruction fetch response if( !m_core[cid]->fetch_unit_response_buffer_full() ) { m_response_fifo.pop_front(); diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h index b9e0bda..278fafc 100644 --- a/src/gpgpu-sim/shader.h +++ b/src/gpgpu-sim/shader.h @@ -105,7 +105,6 @@ #define WRITE_PACKET_SIZE 8 #define WRITE_MASK_SIZE 8 -#define NO_PARTIAL_WRITE (partial_write_mask_t()) //Set a hard limit of 32 CTAs per shader [cuda only has 8] #define MAX_CTA_PER_SHADER 32 @@ -863,15 +862,13 @@ public: void print(FILE *fout) const; private: - void generate_mem_accesses(warp_inst_t &pipe_reg); - bool shared_cycle( warp_inst_t &inst, mem_stage_stall_type &rc_fail, mem_stage_access_type &fail_type); bool constant_cycle( warp_inst_t &inst, mem_stage_stall_type &rc_fail, mem_stage_access_type &fail_type); bool texture_cycle( warp_inst_t &inst, mem_stage_stall_type &rc_fail, mem_stage_access_type &fail_type); bool memory_cycle( warp_inst_t &inst, mem_stage_stall_type &rc_fail, mem_stage_access_type &fail_type); mem_stage_stall_type process_memory_access_queue( cache_t *cache, warp_inst_t &inst ); - mem_fetch *create_data_mem_fetch(warp_inst_t &inst, mem_access_t &access); + mem_fetch *create_data_mem_fetch(const warp_inst_t &inst, const mem_access_t &access); const memory_config *m_memory_config; class shader_memory_interface *m_icnt; diff --git a/src/gpgpu-sim/visualizer.cc b/src/gpgpu-sim/visualizer.cc index 51348d5..730e0c9 100644 --- a/src/gpgpu-sim/visualizer.cc +++ b/src/gpgpu-sim/visualizer.cc @@ -483,7 +483,7 @@ void time_vector_print_interval2gzfile(gzFile outfile) { void time_vector_update(unsigned int uid,int slot ,long int cycle,int type) { if ( (type == RD_REQ) || (type == REPLY_DATA) ) { g_my_time_vector->update_ld( uid, slot,cycle); - } else if ( type == WT_REQ ) { + } else if ( type == WR_REQ ) { g_my_time_vector->update_st( uid, slot,cycle); } else { abort(); @@ -494,7 +494,7 @@ void check_time_vector_update(unsigned int uid,int slot ,long int latency,int ty { if ( (type == RD_REQ) || (type == REPLY_DATA) ) { g_my_time_vector->check_ld_update( uid, slot, latency ); - } else if ( type == WT_REQ ) { + } else if ( type == WR_REQ ) { g_my_time_vector->check_st_update( uid, slot, latency ); } else { abort(); |