diff options
Diffstat (limited to 'src/gpgpu-sim')
| -rw-r--r-- | src/gpgpu-sim/gpu-cache.cc | 4 | ||||
| -rw-r--r-- | src/gpgpu-sim/gpu-cache.h | 19 | ||||
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.cc | 6 | ||||
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.h | 16 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 4 |
5 files changed, 25 insertions, 24 deletions
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 156c174..76f9aef 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -1329,8 +1329,8 @@ enum cache_request_status data_cache::wr_miss_wa_fetch_on_write( if (mf->get_access_byte_mask().count() == m_config.get_atom_sz()) { // if the request writes to the whole cache line/sector, then, write and set - // cache line Modified. and no need to send read request to memory or reserve - // mshr + // cache line Modified. and no need to send read request to memory or + // reserve mshr if (miss_queue_full(0)) { m_stats.inc_fail_stats(mf->get_access_type(), MISS_QUEUE_FULL); diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 647ed7a..d4bc9b4 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -547,13 +547,14 @@ class cache_config { } if (m_alloc_policy == STREAMING) { // For streaming cache, we set the alloc policy to be on-fill to remove - // all line_alloc_fail stalls we set the MSHRs to be equal to max allocated - // cache lines. This is possible by moving TAG to be shared between cache - // line and MSHR enrty (i.e. for each cache line, there is an MSHR rntey - // associated with it) This is the easiest think we can think about to - // model (mimic) L1 streaming cache in Pascal and Volta Based on our - // microbenchmakrs, MSHRs entries have been increasing substantially in - // Pascal and Volta For more information about streaming cache, see: + // all line_alloc_fail stalls we set the MSHRs to be equal to max + // allocated cache lines. This is possible by moving TAG to be shared + // between cache line and MSHR enrty (i.e. for each cache line, there is + // an MSHR rntey associated with it) This is the easiest think we can + // think about to model (mimic) L1 streaming cache in Pascal and Volta + // Based on our microbenchmakrs, MSHRs entries have been increasing + // substantially in Pascal and Volta For more information about streaming + // cache, see: // http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf // https://ieeexplore.ieee.org/document/8344474/ m_is_streaming = true; @@ -1303,9 +1304,9 @@ class baseline_cache : public cache_t { const cache_config &m_config; int m_data_port_occupied_cycles; //< Number of cycle that the data port - //remains used + // remains used int m_fill_port_occupied_cycles; //< Number of cycle that the fill port - //remains used + // remains used }; bandwidth_management m_bandwidth_management; diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index e44ab95..485d42e 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -1224,7 +1224,7 @@ void gpgpu_sim::gpu_print_stat() { partiton_reqs_in_parallel_util_total) / (gpu_sim_cycle_parition_util + gpu_tot_sim_cycle_parition_util)); // printf("partiton_replys_in_parallel = %lld\n", - // partiton_replys_in_parallel); printf("partiton_replys_in_parallel_total = + // partiton_replys_in_parallel); printf("partiton_replys_in_parallel_total = // %lld\n", partiton_replys_in_parallel_total ); printf("L2_BW = %12.4f GB/Sec\n", ((float)(partiton_replys_in_parallel * 32) / @@ -1735,8 +1735,8 @@ void gpgpu_sim::cycle() { m_power_stats->pwr_mem_stat->l2_cache_stats[CURRENT_STAT_IDX].clear(); for (unsigned i = 0; i < m_memory_config->m_n_mem_sub_partition; i++) { // move memory request from interconnect into memory partition (if not - // backed up) Note:This needs to be called in DRAM clock domain if there is - // no L2 cache in the system In the worst case, we may need to push + // backed up) Note:This needs to be called in DRAM clock domain if there + // is no L2 cache in the system In the worst case, we may need to push // SECTOR_CHUNCK_SIZE requests, so ensure you have enough buffer for them if (m_memory_sub_partition[i]->full(SECTOR_CHUNCK_SIZE)) { gpu_stall_dramfull++; diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 9765b38..c75897c 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -263,11 +263,11 @@ class memory_config { // GDDR5 this is identical to RTPS, if for other DRAM this is // different, you will need to split them in two - unsigned tCCD; // column to column delay - unsigned tRRD; // minimal time required between activation of rows in - // different banks - unsigned tRCD; // row to column delay - time required to activate a row - // before a read + unsigned tCCD; // column to column delay + unsigned tRRD; // minimal time required between activation of rows in + // different banks + unsigned tRCD; // row to column delay - time required to activate a row + // before a read unsigned tRCDWR; // row to column delay for a write command unsigned tRAS; // time needed to activate row unsigned tRP; // row precharge ie. deactivate row @@ -275,7 +275,7 @@ class memory_config { tRC; // row cycle time ie. precharge current, then activate different row unsigned tCDLR; // Last data-in to Read command (switching from write to // read) - unsigned tWR; // Last data-in to Row precharge + unsigned tWR; // Last data-in to Row precharge unsigned CL; // CAS latency unsigned WL; // WRITE latency @@ -626,9 +626,9 @@ class gpgpu_sim : public gpgpu_t { std::map<unsigned, watchpoint_event> g_watchpoint_hits; std::string executed_kernel_info_string(); //< format the kernel information - //into a string for stat printout + // into a string for stat printout void clear_executed_kernel_info(); //< clear the kernel information after - //stat printout + // stat printout public: unsigned long long gpu_sim_insn; diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 45e6790..c7738c0 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3426,8 +3426,8 @@ void shader_core_ctx::warp_exit(unsigned warp_id) { for (unsigned i = warp_id * get_config()->warp_size; i < (warp_id + 1) * get_config()->warp_size; i++) { // if(this->m_thread[i]->m_functional_model_thread_state && - //this->m_thread[i].m_functional_model_thread_state->donecycle()==0) { done - //= false; + // this->m_thread[i].m_functional_model_thread_state->donecycle()==0) { + // done = false; // } if (m_thread[i] && !m_thread[i]->is_done()) done = false; |