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Diffstat (limited to 'src/intersim2/examples/flatflyconfig')
| -rw-r--r-- | src/intersim2/examples/flatflyconfig | 116 |
1 files changed, 116 insertions, 0 deletions
diff --git a/src/intersim2/examples/flatflyconfig b/src/intersim2/examples/flatflyconfig new file mode 100644 index 0000000..6674d28 --- /dev/null +++ b/src/intersim2/examples/flatflyconfig @@ -0,0 +1,116 @@ +// $Id: flatflyconfig 5188 2012-08-30 00:31:31Z dub $ + +// Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +//A flattened butterfly configurate file with many tweaks from the +//default settings. + + +// Flow control +// Total number of VCs must match the above assignments +num_vcs = 8; +vc_buf_size = 4; + +wait_for_tail_credit = 0; + +// +// Router architectureq +// +vc_allocator = islip; +sw_allocator = islip; +alloc_iters = 1; + +credit_delay = 2; +routing_delay = 0; +vc_alloc_delay = 1; +sw_alloc_delay = 1; +st_final_delay = 1; + +input_speedup = 1; +output_speedup = 1; +internal_speedup = 1.0; + +// +// Traffic +// + +warmup_periods = 3; + +sample_period = 1000; + +sim_count = 1; + +traffic = uniform; + + +// Flatfly +// +// #node = k^(n+1) +// +// x, y, specifies the arrangement of routers in x and y dim +// xr, yr specifiies the arayment of clients in a router +// +topology = flatfly; +subnets = 1; + +c = 4; +k = 4; +n = 2; + +x = 4; +y = 4; +xr = 2; +yr = 2; + +// +// Routing +// + +routing_function = ran_min; + +//1: batch mode, 0: injection mode +use_read_write = 0; + +//for injection mode +packet_size = 1; +injection_rate = 0.1; + +//for batch mode +read_request_size=1; +write_request_size=1; +read_reply_size=1; +write_reply_size=1; + +read_request_begin_vc = 0; +read_request_end_vc = 3; +write_reply_begin_vc = 4; +write_reply_end_vc = 7; +read_reply_begin_vc = 4; +read_reply_end_vc = 7; +write_request_begin_vc = 0; +write_request_end_vc = 3; + +//latency: drains all packet, throughput:no drain? +sim_type = latency; |
