summaryrefslogtreecommitdiff
path: root/src/intersim2/examples/singleconfig
diff options
context:
space:
mode:
Diffstat (limited to 'src/intersim2/examples/singleconfig')
-rw-r--r--src/intersim2/examples/singleconfig57
1 files changed, 57 insertions, 0 deletions
diff --git a/src/intersim2/examples/singleconfig b/src/intersim2/examples/singleconfig
new file mode 100644
index 0000000..aca3d28
--- /dev/null
+++ b/src/intersim2/examples/singleconfig
@@ -0,0 +1,57 @@
+// $Id: singleconfig 5188 2012-08-30 00:31:31Z dub $
+
+// Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice, this
+// list of conditions and the following disclaimer.
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+
+//A single cross 10X10 cross bar under injection mode
+
+topology = fly;
+
+k = 10;
+n = 1;
+
+num_vcs = 8;
+
+vc_buf_size = 8;
+
+vc_allocator = separable_input_first;
+sw_allocator = separable_input_first;
+
+routing_function = dest_tag;
+
+traffic = uniform;
+
+use_read_write = 0;
+
+injection_rate = 1.0;
+
+
+
+
+sample_period = 100000;
+
+routing_delay = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+st_final_delay = 1;