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-rw-r--r--src/cuda-sim/cuda-sim.cc14
-rw-r--r--src/cuda-sim/instructions.cc13
-rw-r--r--src/cuda-sim/memory.cc8
-rw-r--r--src/cuda-sim/opcodes.def1
-rw-r--r--src/cuda-sim/ptx.l1
-rw-r--r--src/cuda-sim/ptx_ir.cc3
-rw-r--r--src/gpgpu-sim/shader.cc4
7 files changed, 34 insertions, 10 deletions
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 2a41e4b..bf90938 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -555,7 +555,7 @@ void gpgpu_ptx_sim_init_memory()
static bool initialized = false;
if ( !initialized ) {
g_global_mem = new memory_space_impl<8192>("global",64*1024);
- g_param_mem = new memory_space_impl<64>("param",64*1024);
+ g_param_mem = new memory_space_impl<8192>("param",64*1024);
g_tex_mem = new memory_space_impl<8192>("tex",64*1024);
g_surf_mem = new memory_space_impl<8192>("surf",64*1024);
initialized = true;
@@ -992,12 +992,14 @@ void function_info::add_param_name_type_size( unsigned index, std::string name,
void function_info::add_param_data( unsigned argn, struct gpgpu_ptx_sim_arg *args )
{
const void *data = args->m_start;
- param_t tmp;
if( data ) {
+ param_t tmp;
+
tmp.pdata = args->m_start;
tmp.size = args->m_nbytes;
tmp.offset = args->m_offset;
+ tmp.type = 0;
std::map<unsigned,param_info>::iterator i=m_ptx_kernel_param_info.find(argn);
if( i != m_ptx_kernel_param_info.end()) {
i->second.add_data(tmp);
@@ -1139,6 +1141,8 @@ void function_info::ptx_exec_inst( ptx_thread_info *thread,
unsigned index = pc - m_start_PC;
assert( index < m_instr_mem_size );
ptx_instruction *pI = m_instr_mem[index];
+ try {
+
g_current_symbol_table = thread->get_finfo()->get_symtab();
thread->clearRPC();
thread->m_last_set_operand_value.u64 = 0;
@@ -1248,6 +1252,12 @@ void function_info::ptx_exec_inst( ptx_thread_info *thread,
*space = insn_space;
*addr = insn_memaddr;
*data_size = insn_data_size;
+
+ } catch ( int x ) {
+ printf("GPGPU-Sim PTX: ERROR (%d) executing intruction (%s:%u)\n", x, pI->source_file(), pI->source_line() );
+ printf("GPGPU-Sim PTX: '%s'\n", pI->get_source() );
+ abort();
+ }
}
unsigned g_gx, g_gy, g_gz;
diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index a19f1a8..3ce0a2f 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -1452,7 +1452,7 @@ void decode_space( memory_space_t &space, const ptx_thread_info *thread, const o
case surf_space: mem = g_surf_mem; break;
case param_space_kernel: mem = g_param_mem; break;
case shared_space: mem = thread->m_shared_mem; break;
- case const_space: assert(space.get_bank()==0); mem = g_global_mem; break;
+ case const_space: mem = g_global_mem; break;
case generic_space:
if( thread->get_ptx_version().ver() >= 2.0 ) {
// convert generic address to memory space address
@@ -1474,7 +1474,7 @@ void decode_space( memory_space_t &space, const ptx_thread_info *thread, const o
}
}
-void ld_impl( const ptx_instruction *pI, ptx_thread_info *thread )
+void ld_exec( const ptx_instruction *pI, ptx_thread_info *thread )
{
const operand_info &dst = pI->dst();
const operand_info &src1 = pI->src1();
@@ -1515,7 +1515,14 @@ void ld_impl( const ptx_instruction *pI, ptx_thread_info *thread )
thread->m_last_memory_space = space;
}
-void ldu_impl( const ptx_instruction *pI, ptx_thread_info *thread ) { inst_not_implemented(pI); }
+void ld_impl( const ptx_instruction *pI, ptx_thread_info *thread )
+{
+ ld_exec(pI,thread);
+}
+void ldu_impl( const ptx_instruction *pI, ptx_thread_info *thread )
+{
+ ld_exec(pI,thread);
+}
void lg2_impl( const ptx_instruction *pI, ptx_thread_info *thread )
{
diff --git a/src/cuda-sim/memory.cc b/src/cuda-sim/memory.cc
index 754fe7f..09c9e81 100644
--- a/src/cuda-sim/memory.cc
+++ b/src/cuda-sim/memory.cc
@@ -94,7 +94,13 @@ template<unsigned BSIZE> void memory_space_impl<BSIZE>::read( mem_addr_t addr, s
unsigned offset = addr & (BSIZE-1);
unsigned nbytes = length;
typename map_t::const_iterator i = m_data.find(index);
- assert( (addr+length) <= (index+1)*BSIZE );
+ if( (addr+length) > (index+1)*BSIZE ) {
+ printf("GPGPU-Sim PTX: ERROR * access to memory \'%s\' is unaligned : addr=0x%x, length=%zu\n",
+ m_name.c_str(), addr, length);
+ printf("GPGPU-Sim PTX: (addr+length)=0x%lx > 0x%x=(index+1)*BSIZE, index=0x%x, BSIZE=0x%x\n",
+ (addr+length),(index+1)*BSIZE, index, BSIZE);
+ throw 1;
+ }
if( i == m_data.end() ) {
for( size_t n=0; n < length; n++ )
((unsigned char*)data)[n] = (unsigned char) 0;
diff --git a/src/cuda-sim/opcodes.def b/src/cuda-sim/opcodes.def
index 143bb93..4566468 100644
--- a/src/cuda-sim/opcodes.def
+++ b/src/cuda-sim/opcodes.def
@@ -95,6 +95,7 @@ OP_DEF(EXIT_OP,exit_impl,"exit",1,3)
OP_DEF(FMA_OP,fma_impl,"fma",1,2)
OP_DEF(ISSPACEP_OP,isspacep_impl,"isspacep",1,1)
OP_DEF(LD_OP,ld_impl,"ld",1,5)
+OP_DEF(LDU_OP,ldu_impl,"ldu",1,5)
OP_DEF(LG2_OP,lg2_impl,"lg2",1,4)
OP_DEF(MAD24_OP,mad24_impl,"mad24",1,2)
OP_DEF(MAD_OP,mad_impl,"mad",1,2)
diff --git a/src/cuda-sim/ptx.l b/src/cuda-sim/ptx.l
index 3e98a75..3b83e44 100644
--- a/src/cuda-sim/ptx.l
+++ b/src/cuda-sim/ptx.l
@@ -109,6 +109,7 @@ fma TC; ptx_lval.int_value = FMA_OP; return OPCODE;
isspacep TC; ptx_lval.int_value = ISSPACEP_OP; return OPCODE;
ld TC; ptx_lval.int_value = LD_OP; return OPCODE;
ld.volatile TC; ptx_lval.int_value = LD_OP; return OPCODE;
+ldu TC; ptx_lval.int_value = LDU_OP; return OPCODE;
lg2 TC; ptx_lval.int_value = LG2_OP; return OPCODE;
mad24 TC; ptx_lval.int_value = MAD24_OP; return OPCODE;
mad TC; ptx_lval.int_value = MAD_OP; return OPCODE;
diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc
index fa87ad9..cfa6650 100644
--- a/src/cuda-sim/ptx_ir.cc
+++ b/src/cuda-sim/ptx_ir.cc
@@ -419,7 +419,6 @@ void add_identifier( const char *identifier, int array_dim, unsigned array_ident
g_current_symbol_table->alloc_shared( num_bits/8 + addr_pad );
break;
case const_space:
- assert(ti.get_memory_space().get_bank()==0);
if( array_ident == ARRAY_IDENTIFIER_NO_DIM ) {
printf("GPGPU-Sim PTX: deferring allocation of constant region for \"%s\" (need size information)\n", identifier );
} else {
@@ -1363,6 +1362,8 @@ unsigned type_info_key::type_decode( int type, size_t &size, int &basic_type )
case B16_TYPE: size=16; basic_type=0; return 13;
case B32_TYPE: size=32; basic_type=0; return 14;
case B64_TYPE: size=64; basic_type=0; return 15;
+ case TEXREF_TYPE: case SAMPLERREF_TYPE: case SURFREF_TYPE:
+ size=32; basic_type=3; return 16;
default:
printf("ERROR ** type_decode() does not know about \"%s\"\n", g_ptx_token_decode[type].c_str() );
assert(0);
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 4901d51..7a31d15 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -2468,7 +2468,6 @@ mem_stage_stall_type send_mem_request(shader_core_ctx_t *shader, mem_access_t &a
mem_access_type access_type;
switch(access.space.get_type()) {
case const_space:
- assert(access.space.get_bank()==0);
case param_space_kernel:
code = CONSTC;
access_type = CONST_ACC_R;
@@ -2826,7 +2825,6 @@ void shader_memory_queue(shader_core_ctx_t *shader, shader_queues_t *accessqs)
type_counts[SHARED_MEM_PATH]++;
break;
case const_space:
- assert(shader->pipeline_reg[EX_MM][i].space.get_bank()==0);
case param_space_kernel:
path[i] = CONSTANT_MEM_PATH;
type_counts[CONSTANT_MEM_PATH]++;
@@ -2948,7 +2946,7 @@ void register_cta_thread_exit(shader_core_ctx_t *shader, int tid )
shader->n_active_cta--;
shader->deallocate_barrier(cta_num);
shader_CTA_count_unlog(shader->sid, 1);
- printf("Shader %d finished CTA #%d (%lld,%lld)\n", shader->sid, cta_num, gpu_sim_cycle, gpu_tot_sim_cycle );
+ printf("GPGPU-Sim uArch: Shader %d finished CTA #%d (%lld,%lld)\n", shader->sid, cta_num, gpu_sim_cycle, gpu_tot_sim_cycle );
}
}
}
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 09:47:13 +0000