diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.h | 19 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 29 |
2 files changed, 7 insertions, 41 deletions
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 4fa0aaa..bad4adc 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -69,28 +69,23 @@ #ifndef GPU_SIM_H #define GPU_SIM_H -#define NUM_SHADERS 8 -#define STREAMS_PER_FILE 128 - +// constants for statistics printouts #define GPU_RSTAT_SHD_INFO 0x1 #define GPU_RSTAT_BW_STAT 0x2 #define GPU_RSTAT_WARP_DIS 0x4 #define GPU_RSTAT_DWF_MAP 0x8 - -//gpgpu_interwarp_mshr_merge -#define TEX_MSHR_MERGE 0x4 -#define CONST_MSHR_MERGE 0x2 -#define GLOBAL_MSHR_MERGE 0x1 - -//Prints out a verbose L1 miss rate per thread for shader 0 #define GPU_RSTAT_L1MISS 0x10 #define GPU_RSTAT_PDOM 0x20 #define GPU_RSTAT_SCHED 0x40 - -//options for gpgpu_memlatency_stat #define GPU_MEMLATSTAT_MC 0x2 #define GPU_MEMLATSTAT_QUEUELOGS 0x4 +// constants for configuring merging of coalesced scatter-gather requests +#define TEX_MSHR_MERGE 0x4 +#define CONST_MSHR_MERGE 0x2 +#define GLOBAL_MSHR_MERGE 0x1 + +// clock constants #define MhZ *1000000 extern void init_gpu(); diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 28861bf..9373929 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -2898,35 +2898,6 @@ void register_cta_thread_exit(shader_core_ctx_t *shader, int tid ) } } -#if 0 -//this function is unecessary, cache is properly dirtied by fill with cache line function in gpu-sim.cc -void dirty_cache_lines(shader_core_ctx_t *shader, mshr_entry_t* mshr){ - shd_cache_line_t *hit_cacheline; - if (mshr->istexture) { - hit_cacheline = shd_cache_access(shader->L1texcache, - mshr->addr, WORD_SIZE, - mshr->iswrite, //should always be 0 - shader->gpu_cycle); - shd_cache_undo_stats( shader->L1texcache, !hit_cacheline ); - } else if (mshr->isconst) { - hit_cacheline = shd_cache_access(shader->L1constcache, - mshr->addr, WORD_SIZE, - mshr->iswrite, //should always be 0 - shader->gpu_cycle); - shd_cache_undo_stats( shader->L1constcache, !hit_cacheline ); - } else if (!gpgpu_no_dl1) { - hit_cacheline = shd_cache_access(shader->L1cache, - mshr->addr, WORD_SIZE, - mshr->iswrite, - shader->gpu_cycle); - shd_cache_undo_stats( shader->L1constcache, !hit_cacheline ); - if (!hit_cacheline) { - writeback_l1_miss++; - } - } -} -#endif - typedef struct { unsigned pc; unsigned long latency; |