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-rw-r--r--src/gpgpu-sim/addrdec.cc2
-rw-r--r--src/gpgpu-sim/gpu-sim.cc15
-rw-r--r--src/gpgpu-sim/gpu-sim.h4
-rw-r--r--src/gpgpu-sim/shader.cc49
-rw-r--r--src/gpgpu-sim/shader.h2
-rw-r--r--src/trace-driven/gpgpusim_trace_driven_main.cc6
-rw-r--r--src/trace-driven/kepler_opcode.h149
-rw-r--r--src/trace-driven/pascal_opcode.h8
-rw-r--r--src/trace-driven/trace_driven.cc16
-rw-r--r--src/trace-driven/trace_driven.h2
-rw-r--r--src/trace-driven/trace_opcode.h7
11 files changed, 230 insertions, 30 deletions
diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc
index 670bd61..c34cb32 100644
--- a/src/gpgpu-sim/addrdec.cc
+++ b/src/gpgpu-sim/addrdec.cc
@@ -221,7 +221,7 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, addrdec_
{
//This is an unrealistic hashing using software hashtable
//we generate a random set for each memory address and save the value in a big hashtable for future reuse
- assert(!gap);
+ //assert(!gap);
new_addr_type chip_address = (addr>>(ADDR_CHIP_S-log2sub_partition));
tr1_hash_map<new_addr_type,unsigned>::const_iterator got = address_random_interleaving.find (chip_address);
if ( got == address_random_interleaving.end() ) {
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 7f9985e..cd5fa56 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -453,7 +453,7 @@ void shader_core_config::reg_options(class OptionParser * opp)
"1");
option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_INT32, &gpgpu_num_tensor_core_units,
"Number of tensor_core units (default=1)",
- "1");
+ "0");
option_parser_register(opp, "-gpgpu_num_mem_units", OPT_INT32, &gpgpu_num_mem_units,
"Number if ldst units (default=1) WARNING: not hooked up to anything",
"1");
@@ -470,7 +470,12 @@ void shader_core_config::reg_options(class OptionParser * opp)
option_parser_register(opp, "-perfect_inst_const_cache", OPT_BOOL, &perfect_inst_const_cache,
"perfect inst and const cache mode, so all inst and const hits in the cache(default = disabled)",
"0");
-
+ option_parser_register(opp, "-inst_fetch_throughput", OPT_INT32, &inst_fetch_throughput,
+ "the number of fetched intruction per warp each cycle",
+ "1");
+ option_parser_register(opp, "-gpgpu_reg_file_port_throughput", OPT_INT32, &reg_file_port_throughput,
+ "the number ports of the register file",
+ "1");
}
void gpgpu_sim_config::reg_options(option_parser_t opp)
@@ -573,6 +578,9 @@ void gpgpu_sim_config::reg_options(option_parser_t opp)
option_parser_register(opp, "-trace_driven_mode", OPT_BOOL,
&trace_driven_mode, "Turn on trace_driven_mode",
"0");
+ option_parser_register(opp, "-trace_skip_first_kernel", OPT_BOOL,
+ &trace_skip_first_kernel, "skip first intiliztion kernel in trace mode",
+ "0");
option_parser_register(opp, "-trace", OPT_CSTR,
&g_traces_filename, "traces kernel file"
"traces kernel file directory",
@@ -1820,7 +1828,8 @@ void shader_core_ctx::dump_warp_state( FILE *fout ) const
void gpgpu_sim::perf_memcpy_to_gpu( size_t dst_start_addr, size_t count )
{
if (m_memory_config->m_perf_sim_memcpy) {
- assert (dst_start_addr % 32 == 0);
+ //if(!m_config.trace_driven_mode) //in trace-driven mode, CUDA runtime can start nre data structure at any position
+ // assert (dst_start_addr % 32 == 0);
for ( unsigned counter = 0; counter < count; counter += 32 ) {
const unsigned wr_addr = dst_start_addr + counter;
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index 1ac4fdb..abc905e 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -348,7 +348,8 @@ public:
size_t sync_depth_limit() const {return runtime_sync_depth_limit; }
size_t pending_launch_count_limit() const {return runtime_pending_launch_count_limit;}
- unsigned is_trace_driven_mode() const { return trace_driven_mode; }
+ bool is_trace_driven_mode() const { return trace_driven_mode; }
+ bool is_skip_first_kernel() const { return trace_skip_first_kernel; }
char* get_traces_filename() const { return g_traces_filename; }
bool flush_l1() const { return gpgpu_flush_l1_cache; }
@@ -408,6 +409,7 @@ private:
//trace driven mode options
bool trace_driven_mode;
+ bool trace_skip_first_kernel;
char *g_traces_filename;
friend class gpgpu_sim;
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 23050d3..65ec113 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -384,12 +384,12 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
m_fu.push_back(new dp_unit( &m_pipeline_reg[EX_WB], m_config, this ));
m_dispatch_port.push_back(ID_OC_DP);
m_issue_port.push_back(OC_EX_DP);
- }
+ }
for (int k = 0; k < m_config->gpgpu_num_int_units; k++) {
m_fu.push_back(new int_unit( &m_pipeline_reg[EX_WB], m_config, this ));
m_dispatch_port.push_back(ID_OC_INT);
m_issue_port.push_back(OC_EX_INT);
- }
+ }
for (int k = 0; k < m_config->gpgpu_num_sfu_units; k++) {
m_fu.push_back(new sfu( &m_pipeline_reg[EX_WB], m_config, this ));
@@ -1067,7 +1067,15 @@ void scheduler_unit::cycle()
exec_unit_type_t previous_issued_inst_exec_type = exec_unit_type_t::NONE;
unsigned max_issue = m_shader->m_config->gpgpu_max_insn_issue_per_warp;
bool diff_exec_units = m_shader->m_config->gpgpu_dual_issue_diff_exec_units; //In tis mode, we only allow dual issue to diff execution units (as in Maxwell and Pascal)
-
+
+ if(warp(warp_id).ibuffer_empty())
+ SCHED_DPRINTF( "Warp (warp_id %u, dynamic_warp_id %u) fails as ibuffer_empty\n",
+ (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id() );
+
+ if(warp(warp_id).waiting())
+ SCHED_DPRINTF( "Warp (warp_id %u, dynamic_warp_id %u) fails as waiting for barrier\n",
+ (*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id() );
+
while( !warp(warp_id).waiting() && !warp(warp_id).ibuffer_empty() && (checked < max_issue) && (checked <= issued) && (issued < max_issue) ) {
const warp_inst_t *pI = warp(warp_id).ibuffer_next_inst();
//Jin: handle cdp latency;
@@ -1120,13 +1128,13 @@ void scheduler_unit::cycle()
}
} else {
- bool sp_pipe_avail = m_sp_out->has_free(m_shader->m_config->sub_core_model, m_id);
- bool sfu_pipe_avail = m_sfu_out->has_free(m_shader->m_config->sub_core_model, m_id);
- bool tensor_core_pipe_avail = m_tensor_core_out->has_free(m_shader->m_config->sub_core_model, m_id);
- bool dp_pipe_avail = m_dp_out->has_free(m_shader->m_config->sub_core_model, m_id);
- bool int_pipe_avail = m_int_out->has_free(m_shader->m_config->sub_core_model, m_id);
+ bool sp_pipe_avail = (m_shader->m_config->gpgpu_num_sp_units > 0) && m_sp_out->has_free(m_shader->m_config->sub_core_model, m_id);
+ bool sfu_pipe_avail = (m_shader->m_config->gpgpu_num_sfu_units > 0) && m_sfu_out->has_free(m_shader->m_config->sub_core_model, m_id);
+ bool tensor_core_pipe_avail = (m_shader->m_config->gpgpu_num_tensor_core_units > 0) && m_tensor_core_out->has_free(m_shader->m_config->sub_core_model, m_id);
+ bool dp_pipe_avail = (m_shader->m_config->gpgpu_num_dp_units > 0) && m_dp_out->has_free(m_shader->m_config->sub_core_model, m_id);
+ bool int_pipe_avail = (m_shader->m_config->gpgpu_num_int_units > 0) && m_int_out->has_free(m_shader->m_config->sub_core_model, m_id);
- //This code need to be refactored
+ //This code needs to be refactored
if(pI->op != TENSOR_CORE_OP && pI->op != SFU_OP && pI->op != DP_OP) {
bool execute_on_SP = false;
@@ -1196,7 +1204,7 @@ void scheduler_unit::cycle()
previous_issued_inst_exec_type = exec_unit_type_t::SFU;
}
}
- else if ( (pI->op == TENSOR_CORE_OP) && !(diff_exec_units && previous_issued_inst_exec_type == exec_unit_type_t::SP) ) {
+ else if ( (pI->op == TENSOR_CORE_OP) && !(diff_exec_units && previous_issued_inst_exec_type == exec_unit_type_t::TENSOR) ) {
if( tensor_core_pipe_avail ) {
m_shader->issue_warp(*m_tensor_core_out,pI,active_mask,warp_id,m_id);
issued++;
@@ -2405,7 +2413,8 @@ void ldst_unit::issue( register_set &reg_set )
void ldst_unit::cycle()
{
writeback();
- m_operand_collector->step();
+ for(int i=0; i< m_config->reg_file_port_throughput; ++i)
+ m_operand_collector->step();
for( unsigned stage=0; (stage+1)<m_pipeline_depth; stage++ )
if( m_pipeline_reg[stage]->empty() && !m_pipeline_reg[stage+1]->empty() )
move_warp(m_pipeline_reg[stage], m_pipeline_reg[stage+1]);
@@ -3082,7 +3091,7 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const
case VOLTA: {
//For Volta, we assign the remaining shared memory to L1 cache
//For more info about adaptive cache, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
- assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared
+ //assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared
//To Do: make it flexible and not tuned to 9KB share memory
unsigned max_assoc = m_L1D_config.get_max_assoc();
@@ -3167,8 +3176,10 @@ void shader_core_ctx::cycle()
execute();
read_operands();
issue();
- decode();
- fetch();
+ for(int i=0; i< m_config->inst_fetch_throughput; ++i) {
+ decode();
+ fetch();
+ }
}
// Flushes all content of the cache to memory
@@ -3224,9 +3235,10 @@ std::list<opndcoll_rfu_t::op_t> opndcoll_rfu_t::arbiter_t::allocate_reads()
///// wavefront allocator from booksim... --->
// Loop through diagonals of request matrix
+ // printf("####\n");
for ( int p = 0; p < _square; ++p ) {
- output = ( _pri + p ) % _square;
+ output = ( _pri + p ) % _outputs;
// Step through the current diagonal
for ( input = 0; input < _inputs; ++input ) {
@@ -3234,19 +3246,20 @@ std::list<opndcoll_rfu_t::op_t> opndcoll_rfu_t::arbiter_t::allocate_reads()
assert( output < _outputs );
if ( ( output < _outputs ) &&
( _inmatch[input] == -1 ) &&
- ( _outmatch[output] == -1 ) &&
+ //( _outmatch[output] == -1 ) && //allow OC to read multiple reg banks at the same cycle
( _request[input][output]/*.label != -1*/ ) ) {
// Grant!
_inmatch[input] = output;
_outmatch[output] = input;
+ // printf("Register File: granting bank %d to OC %d, schedid %d, warpid %d, Regid %d\n", input, output, (m_queue[input].front()).get_sid(), (m_queue[input].front()).get_wid(), (m_queue[input].front()).get_reg());
}
- output = ( output + 1 ) % _square;
+ output = ( output + 1 ) % _outputs;
}
}
// Round-robin the priority diagonal
- _pri = ( _pri + 1 ) % _square;
+ _pri = ( _pri + 1 ) % _outputs;
/// <--- end code from booksim
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index d41c220..665e3a5 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1524,6 +1524,8 @@ class shader_core_config : public core_config
bool gpgpu_concurrent_kernel_sm;
bool perfect_inst_const_cache;
+ unsigned inst_fetch_throughput;
+ unsigned reg_file_port_throughput;
};
diff --git a/src/trace-driven/gpgpusim_trace_driven_main.cc b/src/trace-driven/gpgpusim_trace_driven_main.cc
index 0385f51..bedac4c 100644
--- a/src/trace-driven/gpgpusim_trace_driven_main.cc
+++ b/src/trace-driven/gpgpusim_trace_driven_main.cc
@@ -50,6 +50,7 @@ int main ( int argc, const char **argv )
trace_parser tracer(m_gpgpu_sim->get_config().get_traces_filename(), m_gpgpu_sim, m_gpgpu_context);
std::vector<std::string> commandlist = tracer.parse_kernellist_file();
+ bool first_kernel=true;
for(unsigned i=0; i<commandlist.size(); ++i) {
@@ -63,6 +64,11 @@ int main ( int argc, const char **argv )
continue;
}
else {
+ //skip the first unimportant initialization kernel
+ if(m_gpgpu_sim->get_config().is_skip_first_kernel() && first_kernel) {
+ first_kernel = false;
+ continue;
+ }
kernel_info = tracer.parse_kernel_info(commandlist[i]);
m_gpgpu_sim->launch(kernel_info);
}
diff --git a/src/trace-driven/kepler_opcode.h b/src/trace-driven/kepler_opcode.h
new file mode 100644
index 0000000..f2bbc90
--- /dev/null
+++ b/src/trace-driven/kepler_opcode.h
@@ -0,0 +1,149 @@
+//developed by Mahmoud Khairy, Purdue Univ
+//[email protected]
+
+#ifndef KEPLER_OPCODE_H
+#define KEPLER_OPCODE_H
+
+#include "../abstract_hardware_model.h"
+#include "trace_opcode.h"
+#include <unordered_map>
+#include <string>
+
+#define KEPLER_BINART_VERSION 35
+#define KEPLER_SHARED_MEMORY_VIRTIAL_ADDRESS_START 0x00007f2c60000000
+
+//TO DO: moving this to a yml or def files
+
+///Kepler ISA
+//see: https://docs.nvidia.com/cuda/cuda-binary-utilities/index.html
+static const std::unordered_map<std::string,OpcodeChar> Kepler_OpcodeMap = {
+ //Floating Point 32 Instructions
+ {"FFMA", OpcodeChar(OP_FFMA, SP_OP)},
+ {"FFMA32I", OpcodeChar(OP_FFMA32I, SP_OP)},
+ {"FADD", OpcodeChar(OP_FADD, SP_OP)},
+ {"FADD32I", OpcodeChar(OP_FADD32I, SP_OP)},
+ {"FCMP", OpcodeChar(OP_FCMP, SP_OP)},
+ {"FMUL", OpcodeChar(OP_FMUL, SP_OP)},
+ {"FMUL32I", OpcodeChar(OP_FMUL32I, SP_OP)},
+ {"FMNMX", OpcodeChar(OP_FMNMX, SP_OP)},
+ {"FSWZ", OpcodeChar(OP_FSWZ, SP_OP)},
+ {"FSET", OpcodeChar(OP_FSET, SP_OP)},
+ {"FSETP", OpcodeChar(OP_FSETP, SP_OP)},
+ {"FCHK", OpcodeChar(OP_FCHK, SP_OP)},
+ {"RRO", OpcodeChar(OP_RRO, SP_OP)},
+ //SFU
+ {"MUFU", OpcodeChar(OP_MUFU, SFU_OP)},
+
+
+ //Double Point Instructions
+ {"DFMA", OpcodeChar(OP_DFMA, DP_OP)},
+ {"DADD", OpcodeChar(OP_DADD, DP_OP)},
+ {"DMUL", OpcodeChar(OP_DMUL, DP_OP)},
+ {"DMNMX", OpcodeChar(OP_DMNMX, DP_OP)},
+ {"DSET", OpcodeChar(OP_DSET, DP_OP)},
+ {"DSETP", OpcodeChar(OP_DSETP, DP_OP)},
+
+ //Integer Instructions
+ {"IMAD", OpcodeChar(OP_IMAD, INTP_OP)},
+ {"IMADSP", OpcodeChar(OP_IMADSP, INTP_OP)},
+ {"IMUL", OpcodeChar(OP_IMUL, INTP_OP)},
+ {"IMUL32I", OpcodeChar(OP_IMUL32I, INTP_OP)},
+ {"IADD", OpcodeChar(OP_IADD, INTP_OP)},
+ {"IADD32I", OpcodeChar(OP_IADD32I, INTP_OP)},
+ {"ISUB", OpcodeChar(OP_ISUB, INTP_OP)},
+ {"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)},
+ {"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)},
+ {"ISAD", OpcodeChar(OP_ISAD, INTP_OP)},
+ {"IMNMX", OpcodeChar(OP_IMNMX, INTP_OP)},
+ {"BFE", OpcodeChar(OP_BFE, INTP_OP)},
+ {"BFI", OpcodeChar(OP_BFI, INTP_OP)},
+ {"SHR", OpcodeChar(OP_SHR, INTP_OP)},
+ {"SHL", OpcodeChar(OP_SHL, INTP_OP)},
+ {"SHF", OpcodeChar(OP_SHF, INTP_OP)},
+ {"LOP", OpcodeChar(OP_LOP, INTP_OP)},
+ {"LOP32I", OpcodeChar(OP_LOP32I, INTP_OP)},
+ {"FLO", OpcodeChar(OP_FLO, INTP_OP)},
+ {"ISET", OpcodeChar(OP_ISET, INTP_OP)},
+ {"ISETP", OpcodeChar(OP_ISETP, INTP_OP)},
+ {"ICMP", OpcodeChar(OP_ICMP, INTP_OP)},
+ {"POPC", OpcodeChar(OP_POPC, INTP_OP)},
+
+ //Conversion Instructions
+ {"F2F", OpcodeChar(OP_F2F, ALU_OP)},
+ {"F2I", OpcodeChar(OP_F2I, ALU_OP)},
+ {"I2F", OpcodeChar(OP_I2F, ALU_OP)},
+ {"I2I", OpcodeChar(OP_I2I, ALU_OP)},
+
+ //Movement Instructions
+ {"MOV", OpcodeChar(OP_MOV, ALU_OP)},
+ {"MOV32I", OpcodeChar(OP_MOV32I, ALU_OP)},
+ {"SEL", OpcodeChar(OP_SEL, ALU_OP)},
+ {"PRMT", OpcodeChar(OP_PRMT, ALU_OP)},
+ {"SHFL", OpcodeChar(OP_SHFL, ALU_OP)},
+
+ //Predicate Instructions
+ {"P2R", OpcodeChar(OP_P2R, ALU_OP)},
+ {"R2P", OpcodeChar(OP_R2P, ALU_OP)},
+ {"CSET", OpcodeChar(OP_CSET, ALU_OP)},
+ {"CSETP", OpcodeChar(OP_CSETP, ALU_OP)},
+ {"PSET", OpcodeChar(OP_PSET, ALU_OP)},
+ {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)},
+
+ //Texture Instructions
+ //For now, we ignore texture loads, consider it as ALU_OP
+ {"TEX", OpcodeChar(OP_TEX, ALU_OP)},
+ {"TLD", OpcodeChar(OP_TLD, ALU_OP)},
+ {"TLD4", OpcodeChar(OP_TLD4, ALU_OP)},
+ {"TXQ", OpcodeChar(OP_TXQ, ALU_OP)},
+
+ //Load/Store Instructions
+ //For now, we ignore constant loads, consider it as ALU_OP, TO DO
+ {"LDC", OpcodeChar(OP_LDC, ALU_OP)},
+ {"LD", OpcodeChar(OP_LD, LOAD_OP)},
+ {"LDG", OpcodeChar(OP_LDG, LOAD_OP)},
+ {"LDL", OpcodeChar(OP_LDL, LOAD_OP)},
+ {"LDS", OpcodeChar(OP_LDS, LOAD_OP)},
+ {"LDSLK", OpcodeChar(OP_LDSLK, LOAD_OP)},
+ {"ST", OpcodeChar(OP_ST, STORE_OP)},
+ {"STL", OpcodeChar(OP_STL, STORE_OP)},
+ {"STS", OpcodeChar(OP_STS, STORE_OP)},
+ {"STSCUL", OpcodeChar(OP_STSCUL, STORE_OP)},
+ {"ATOM", OpcodeChar(OP_ATOM, STORE_OP)},
+ {"RED", OpcodeChar(OP_RED, STORE_OP)},
+ {"CCTL", OpcodeChar(OP_CCTL, ALU_OP)},
+ {"CCTLL", OpcodeChar(OP_CCTLL, ALU_OP)},
+ {"MEMBAR", OpcodeChar(OP_MEMBAR, MEMORY_BARRIER_OP)},
+
+ //surface memory instructions
+ {"SUCLAMP", OpcodeChar(OP_SUCLAMP, LOAD_OP)},
+ {"SUBFM", OpcodeChar(OP_SUBFM, LOAD_OP)},
+ {"SUEAU", OpcodeChar(OP_SUEAU, LOAD_OP)},
+ {"SULDGA", OpcodeChar(OP_SULDGA, LOAD_OP)},
+ {"SUSTGA", OpcodeChar(OP_SUSTGA, STORE_OP)},
+
+ //Control Instructions
+ {"BRA", OpcodeChar(OP_BRA, BRANCH_OP)},
+ {"BRX", OpcodeChar(OP_BRX, BRANCH_OP)},
+ {"JMP", OpcodeChar(OP_JMP, BRANCH_OP)},
+ {"JMX", OpcodeChar(OP_JMX, BRANCH_OP)},
+ {"CAL", OpcodeChar(OP_CAL, CALL_OPS)},
+ {"JCAL", OpcodeChar(OP_JCAL, CALL_OPS)},
+ {"RET", OpcodeChar(OP_RET, RET_OPS)},
+ {"BRK", OpcodeChar(OP_BRK, RET_OPS)},
+ {"CONT", OpcodeChar(OP_CONT, RET_OPS)},
+ {"SSY", OpcodeChar(OP_SSY, RET_OPS)},
+ {"PBK", OpcodeChar(OP_PBK, RET_OPS)},
+ {"PCNT", OpcodeChar(OP_PCNT, RET_OPS)},
+ {"PRET", OpcodeChar(OP_PRET, RET_OPS)},
+ {"BPT", OpcodeChar(OP_BPT, BRANCH_OP)},
+ {"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)},
+
+ //Miscellaneous Instructions
+ {"NOP", OpcodeChar(OP_NOP, ALU_OP)},
+ {"S2R", OpcodeChar(OP_S2R, ALU_OP)},
+ {"B2R", OpcodeChar(OP_B2R, ALU_OP)},
+ {"BAR", OpcodeChar(OP_BAR, BARRIER_OP)},
+ {"VOTE", OpcodeChar(OP_VOTE, ALU_OP)},
+};
+
+#endif
diff --git a/src/trace-driven/pascal_opcode.h b/src/trace-driven/pascal_opcode.h
index d4f787d..2cacb28 100644
--- a/src/trace-driven/pascal_opcode.h
+++ b/src/trace-driven/pascal_opcode.h
@@ -70,6 +70,7 @@ static const std::unordered_map<std::string,OpcodeChar> Pascal_OpcodeMap = {
{"ISCADD", OpcodeChar(OP_ISCADD, INTP_OP)},
{"ISCADD32I", OpcodeChar(OP_ISCADD32I, INTP_OP)},
{"ISETP", OpcodeChar(OP_ISETP, INTP_OP)},
+ {"ISET", OpcodeChar(OP_ISET, INTP_OP)},
{"LEA", OpcodeChar(OP_LEA, INTP_OP)},
{"LOP", OpcodeChar(OP_LOP, INTP_OP)},
{"LOP3", OpcodeChar(OP_LOP3, INTP_OP)},
@@ -85,6 +86,8 @@ static const std::unordered_map<std::string,OpcodeChar> Pascal_OpcodeMap = {
{"IMADSP", OpcodeChar(OP_IMADSP, INTP_OP)},
{"SHL", OpcodeChar(OP_SHL, INTP_OP)},
{"XMAD", OpcodeChar(OP_XMAD, INTP_OP)},
+ {"VMNMX", OpcodeChar(OP_VMNMX, INTP_OP)},
+
//Conversion Instructions
{"F2F", OpcodeChar(OP_F2F, ALU_OP)},
@@ -109,7 +112,8 @@ static const std::unordered_map<std::string,OpcodeChar> Pascal_OpcodeMap = {
{"R2P", OpcodeChar(OP_R2P, ALU_OP)},
{"CSET", OpcodeChar(OP_CSET, ALU_OP)},
{"CSETP", OpcodeChar(OP_CSETP, ALU_OP)},
- {"PSETP", OpcodeChar(OP_PSETP, ALU_OP)},
+ {"PSET", OpcodeChar(OP_PSET, ALU_OP)},
+
//Load/Store Instructions
{"LD", OpcodeChar(OP_LD, LOAD_OP)},
@@ -157,6 +161,8 @@ static const std::unordered_map<std::string,OpcodeChar> Pascal_OpcodeMap = {
{"CALL", OpcodeChar(OP_CALL, CALL_OPS)},
{"EXIT", OpcodeChar(OP_EXIT, EXIT_OPS)},
{"JMP", OpcodeChar(OP_JMP, BRANCH_OP)},
+ {"SSY", OpcodeChar(OP_SSY, BRANCH_OP)},
+ {"SYNC", OpcodeChar(OP_SYNC, BRANCH_OP)},
{"JMX", OpcodeChar(OP_JMX, BRANCH_OP)},
{"KILL", OpcodeChar(OP_KILL, BRANCH_OP)},
{"NANOSLEEP", OpcodeChar(OP_NANOSLEEP, BRANCH_OP)},
diff --git a/src/trace-driven/trace_driven.cc b/src/trace-driven/trace_driven.cc
index fb8afdd..35e953e 100644
--- a/src/trace-driven/trace_driven.cc
+++ b/src/trace-driven/trace_driven.cc
@@ -23,6 +23,7 @@
#include "volta_opcode.h"
#include "turing_opcode.h"
#include "pascal_opcode.h"
+#include "kepler_opcode.h"
#include "../gpgpusim_entrypoint.h"
@@ -221,6 +222,10 @@ trace_kernel_info_t::trace_kernel_info_t(dim3 gridDim, dim3 blockDim, unsigned m
OpcodeMap = &Volta_OpcodeMap;
else if(m_binary_verion == PASCAL_TITANX_BINART_VERSION || m_binary_verion == PASCAL_P100_BINART_VERSION)
OpcodeMap = &Pascal_OpcodeMap;
+ else if(m_binary_verion == KEPLER_BINART_VERSION)
+ OpcodeMap = &Kepler_OpcodeMap;
+ else if(m_binary_verion == TURING_BINART_VERSION)
+ OpcodeMap = &Turing_OpcodeMap;
else
assert(0 && "unsupported binary version");
}
@@ -281,7 +286,7 @@ bool trace_kernel_info_t::get_next_threadblock_traces(std::vector<std::vector<tr
else {
assert(start_of_tb_stream_found);
trace_warp_inst_t inst(m_gpgpu_sim->getShaderCoreConfig(), m_gpgpu_context);
- inst.parse_from_string(line, OpcodeMap);
+ inst.parse_from_string(line, OpcodeMap, binary_verion);
threadblock_traces[warp_id]->push_back(inst);
}
}
@@ -318,7 +323,7 @@ unsigned trace_warp_inst_t::get_datawidth_from_opcode(const std::vector<std::str
return 4; //default is 4 bytes
}
-bool trace_warp_inst_t::parse_from_string(std::string trace, const std::unordered_map<std::string,OpcodeChar>* OpcodeMap){
+bool trace_warp_inst_t::parse_from_string(std::string trace, const std::unordered_map<std::string,OpcodeChar>* OpcodeMap, unsigned binary_verion){
std::stringstream ss;
ss.str(trace);
@@ -541,9 +546,12 @@ bool trace_warp_inst_t::parse_from_string(std::string trace, const std::unordere
case OP_LD:
//TO DO: set generic load based on the address
//right now, we consider all loads are shared.
- assert(mem_width>0);
+ assert(mem_width>0);
data_size = get_datawidth_from_opcode(opcode_tokens);
- space.set_type(shared_space);
+ if(binary_verion == KEPLER_BINART_VERSION)
+ space.set_type(global_space);
+ else
+ space.set_type(shared_space);
if(m_opcode == OP_LD)
memory_op = memory_load;
else
diff --git a/src/trace-driven/trace_driven.h b/src/trace-driven/trace_driven.h
index 33f4baf..9539e6d 100644
--- a/src/trace-driven/trace_driven.h
+++ b/src/trace-driven/trace_driven.h
@@ -44,7 +44,7 @@ public:
m_opcode=0;
}
- bool parse_from_string(std::string trace, const std::unordered_map<std::string,OpcodeChar>* OpcodeMap);
+ bool parse_from_string(std::string trace, const std::unordered_map<std::string,OpcodeChar>* OpcodeMap, unsigned binary_verion);
private:
void set_latency(unsigned cat);
diff --git a/src/trace-driven/trace_opcode.h b/src/trace-driven/trace_opcode.h
index 2b40ace..3492fd3 100644
--- a/src/trace-driven/trace_opcode.h
+++ b/src/trace-driven/trace_opcode.h
@@ -10,6 +10,7 @@
enum TraceInstrOpcode {
+ //volta (common insts for others cards as well)
OP_FADD = 1, OP_FADD32I, OP_FCHK, OP_FFMA32I, OP_FFMA, OP_FMNMX, OP_FMUL, OP_FMUL32I, OP_FSEL, OP_FSET, OP_FSETP,
OP_FSWZADD, OP_MUFU, OP_HADD2, OP_HADD2_32I, OP_HFMA2, OP_HFMA2_32I, OP_HMUL2, OP_HMUL2_32I, OP_HSET2, OP_HSETP2,
OP_HMMA, OP_DADD, OP_DFMA, OP_DMUL, OP_DSETP,
@@ -23,8 +24,12 @@ enum TraceInstrOpcode {
OP_TMML, OP_TXD, OP_TXQ, OP_BMOV, OP_BPT, OP_BRA, OP_BREAK, OP_BRX, OP_BSSY, OP_BSYNC, OP_CALL, OP_EXIT, OP_JMP, OP_JMX,
OP_KILL, OP_NANOSLEEP, OP_RET, OP_RPCMOV, OP_RTT, OP_WARPSYNC, OP_YIELD, OP_B2R, OP_BAR, OP_CS2R, OP_CSMTEST, OP_DEPBAR,
OP_GETLMEMBASE, OP_LEPC, OP_NOP, OP_PMTRIG, OP_R2B, OP_S2R, OP_SETCTAID, OP_SETLMEMBASE, OP_VOTE, OP_VOTE_VTG,
+ //unique insts for pascal
OP_RRO, OP_DMNMX, OP_DSET, OP_BFE, OP_BFI, OP_ICMP, OP_IMADSP, OP_SHL, OP_XMAD, OP_CSET, OP_CSETP,
- OP_TEXS, OP_TLD4S, OP_TLDS, OP_CAL, OP_JCAL, OP_PRET, OP_BRK, OP_PBK, OP_CONT, OP_PCNT, OP_PEXIT,
+ OP_TEXS, OP_TLD4S, OP_TLDS, OP_CAL, OP_JCAL, OP_PRET, OP_BRK, OP_PBK, OP_CONT, OP_PCNT, OP_PEXIT, OP_SSY, OP_SYNC, OP_PSET
+ , OP_VMNMX, OP_ISET,
+ //unique insts for kepler
+ OP_FCMP, OP_FSWZ, OP_ISAD, OP_LDSLK, OP_STSCUL, OP_SUCLAMP, OP_SUBFM, OP_SUEAU, OP_SULDGA, OP_SUSTGA, OP_ISUB,
SASS_NUM_OPCODES /* The total number of opcodes. */
};
typedef enum TraceInstrOpcode sass_op_type;
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 09:58:11 +0000