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-rw-r--r--src/abstract_hardware_model.cc8
-rw-r--r--src/abstract_hardware_model.h6
-rw-r--r--src/cuda-sim/Makefile4
-rw-r--r--src/cuda-sim/cuda-sim.cc18
-rw-r--r--src/cuda-sim/cuda_device_runtime.cc4
-rw-r--r--src/cuda-sim/memory.cc8
-rw-r--r--src/cuda-sim/ptx_ir.cc2
-rw-r--r--src/cuda-sim/ptx_loader.cc6
-rw-r--r--src/cuda-sim/ptx_parser.cc6
-rw-r--r--src/cuda-sim/ptx_sim.cc2
-rw-r--r--src/debug.cc8
-rw-r--r--src/gpgpu-sim/addrdec.cc2
-rw-r--r--src/gpgpu-sim/gpu-cache.h22
-rw-r--r--src/gpgpu-sim/gpu-sim.cc16
-rw-r--r--src/gpgpu-sim/local_interconnect.cc14
-rw-r--r--src/gpgpu-sim/power_interface.cc10
-rw-r--r--src/gpgpu-sim/shader.cc24
-rw-r--r--src/gpgpu-sim/shader.h18
-rw-r--r--src/gpgpu-sim/stat-tool.cc2
-rw-r--r--src/intersim2/networks/anynet.cpp2
-rw-r--r--src/intersim2/networks/kncube.cpp2
-rw-r--r--src/intersim2/networks/qtree.cpp2
-rw-r--r--src/intersim2/vc.cpp2
-rw-r--r--src/stream_manager.h2
24 files changed, 104 insertions, 86 deletions
diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index fda84e8..ed7347d 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -75,7 +75,7 @@ void checkpoint::load_global_mem(class memory_space *temp_mem, char *f1name) {
FILE *fp2 = fopen(f1name, "r");
assert(fp2 != NULL);
char line[128]; /* or other suitable maximum line size */
- unsigned int offset;
+ unsigned int offset = 0;
while (fgets(line, sizeof line, fp2) != NULL) /* read a line */
{
unsigned int index;
@@ -1006,13 +1006,13 @@ void simt_stack::print(FILE *fout) const {
}
for (unsigned j = 0; j < m_warp_size; j++)
fprintf(fout, "%c", (stack_entry.m_active_mask.test(j) ? '1' : '0'));
- fprintf(fout, " pc: 0x%03x", stack_entry.m_pc);
+ fprintf(fout, " pc: 0x%03llx", stack_entry.m_pc);
if (stack_entry.m_recvg_pc == (unsigned)-1) {
fprintf(fout, " rp: ---- tp: %s cd: %2u ",
(stack_entry.m_type == STACK_ENTRY_TYPE_CALL ? "C" : "N"),
stack_entry.m_calldepth);
} else {
- fprintf(fout, " rp: %4u tp: %s cd: %2u ", stack_entry.m_recvg_pc,
+ fprintf(fout, " rp: %4llu tp: %s cd: %2u ", stack_entry.m_recvg_pc,
(stack_entry.m_type == STACK_ENTRY_TYPE_CALL ? "C" : "N"),
stack_entry.m_calldepth);
}
@@ -1032,7 +1032,7 @@ void simt_stack::print_checkpoint(FILE *fout) const {
for (unsigned j = 0; j < m_warp_size; j++)
fprintf(fout, "%c ", (stack_entry.m_active_mask.test(j) ? '1' : '0'));
- fprintf(fout, "%d %d %d %lld %d ", stack_entry.m_pc,
+ fprintf(fout, "%llu %d %llu %lld %d ", stack_entry.m_pc,
stack_entry.m_calldepth, stack_entry.m_recvg_pc,
stack_entry.m_branch_div_cycle, stack_entry.m_type);
fprintf(fout, "%d %d\n", m_warp_id, m_warp_size);
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 6e4a87d..3b95829 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -963,7 +963,7 @@ class inst_t {
}
bool valid() const { return m_decoded; }
virtual void print_insn(FILE *fp) const {
- fprintf(fp, " [inst @ pc=0x%04x] ", pc);
+ fprintf(fp, " [inst @ pc=0x%04llx] ", pc);
}
bool is_load() const {
return (op == LOAD_OP || op == TENSOR_CORE_LOAD_OP ||
@@ -1157,7 +1157,7 @@ class warp_inst_t : public inst_t {
// accessors
virtual void print_insn(FILE *fp) const {
- fprintf(fp, " [inst @ pc=0x%04x] ", pc);
+ fprintf(fp, " [inst @ pc=0x%04llx] ", pc);
for (int i = (int)m_config->warp_size - 1; i >= 0; i--)
fprintf(fp, "%c", ((m_warp_active_mask[i]) ? '1' : '0'));
}
@@ -1386,7 +1386,7 @@ class register_set {
assert(has_ready());
warp_inst_t **ready;
ready = NULL;
- unsigned reg_id;
+ unsigned reg_id = 0;
for (unsigned i = 0; i < regs.size(); i++) {
if (not regs[i]->empty()) {
if (ready and (*ready)->get_uid() < regs[i]->get_uid()) {
diff --git a/src/cuda-sim/Makefile b/src/cuda-sim/Makefile
index 85d1c8c..01bc480 100644
--- a/src/cuda-sim/Makefile
+++ b/src/cuda-sim/Makefile
@@ -129,9 +129,9 @@ $(OUTPUT_DIR)/instructions.h: instructions.cc
$(OUTPUT_DIR)/ptx_parser_decode.def: $(OUTPUT_DIR)/ptx.tab.c
ifeq ($(shell uname),Linux)
- cat $(OUTPUT_DIR)/ptx.tab.h | grep "=" | sed 's/^[ ]\+//' | sed 's/[=,]//g' | sed 's/\([_A-Z1-9]\+\)[ ]\+\([0-9]\+\)/\1 \1/' | sed 's/^/DEF(/' | sed 's/ /,"/' | sed 's/$$/")/' > $(OUTPUT_DIR)/ptx_parser_decode.def
+ cat $(OUTPUT_DIR)/ptx.tab.h | grep "=" | sed 's/^[ ]\+//' | sed -E 's/\s+\/\*.+\*\///' | sed 's/[=,]//g' | sed 's/\([_A-Z1-9]\+\)[ ]\+\([0-9]\+\)/\1 \1/' | sed 's/^/DEF(/' | sed 's/ /,"/' | sed 's/$$/")/' | sed '/YYerror/d;/YYEOF/d;/YYEMPTY/d;/YYUNDEF/d;'> $(OUTPUT_DIR)/ptx_parser_decode.def
else
- cat $(OUTPUT_DIR)/ptx.tab.h | grep "=" | sed -E 's/^ +//' | sed 's/[=,]//g' | sed -E 's/([_A-Z1-9]+).*/\1 \1/' | sed 's/^/DEF(/' | sed 's/ /,"/' | sed 's/$$/")/' > $(OUTPUT_DIR)/ptx_parser_decode.def
+ cat $(OUTPUT_DIR)/ptx.tab.h | grep "=" | sed -E 's/^ +//' | sed -E 's/\s+\/\*.+\*\///' | sed 's/[=,]//g' | sed -E 's/([_A-Z1-9]+).*/\1 \1/' | sed 's/^/DEF(/' | sed 's/ /,"/' | sed 's/$$/")/' | sed '/YYerror/d;/YYEOF/d;/YYEMPTY/d;/YYUNDEF/d;' > $(OUTPUT_DIR)/ptx_parser_decode.def
endif
$(OUTPUT_DIR)/instructions.o: $(OUTPUT_DIR)/instructions.h $(OUTPUT_DIR)/ptx.tab.c
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 680ce79..b063512 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -545,7 +545,7 @@ void gpgpu_t::gpu_memset(size_t dst_start_addr, int c, size_t count) {
void cuda_sim::ptx_print_insn(address_type pc, FILE *fp) {
std::map<unsigned, function_info *>::iterator f = g_pc_to_finfo.find(pc);
if (f == g_pc_to_finfo.end()) {
- fprintf(fp, "<no instruction at address 0x%x>", pc);
+ fprintf(fp, "<no instruction at address 0x%llx>", pc);
return;
}
function_info *finfo = f->second;
@@ -559,7 +559,7 @@ std::string cuda_sim::ptx_get_insn_str(address_type pc) {
#define STR_SIZE 255
char buff[STR_SIZE];
buff[STR_SIZE - 1] = '\0';
- snprintf(buff, STR_SIZE, "<no instruction at address 0x%x>", pc);
+ snprintf(buff, STR_SIZE, "<no instruction at address 0x%llx>", pc);
return std::string(buff);
}
function_info *finfo = f->second;
@@ -1372,7 +1372,7 @@ void function_info::add_param_data(unsigned argn,
unsigned num_bits = 8 * args->m_nbytes;
printf(
"GPGPU-Sim PTX: deferred allocation of shared region for \"%s\" from "
- "0x%x to 0x%x (shared memory space)\n",
+ "0x%llx to 0x%llx (shared memory space)\n",
p->name().c_str(), m_symtab->get_shared_next(),
m_symtab->get_shared_next() + num_bits / 8);
fflush(stdout);
@@ -1503,7 +1503,7 @@ void function_info::list_param(FILE *fout) const {
std::string name = p.get_name();
symbol *param = m_symtab->lookup(name.c_str());
addr_t param_addr = param->get_address();
- fprintf(fout, "%s: %#08x\n", name.c_str(), param_addr);
+ fprintf(fout, "%s: %#08llx\n", name.c_str(), param_addr);
}
fflush(fout);
}
@@ -1533,7 +1533,11 @@ void function_info::ptx_jit_config(
filename_c.c_str());
assert(system(buff) != NULL);
FILE *fp = fopen(filename_c.c_str(), "r");
- fgets(buff, 1024, fp);
+ char * ptr = fgets(buff, 1024, fp);
+ if(ptr == NULL ){
+ printf("can't read file %s \n", filename_c.c_str());
+ assert(0);
+ }
fclose(fp);
std::string fn(buff);
size_t pos1, pos2;
@@ -1877,7 +1881,7 @@ void ptx_thread_info::ptx_exec_inst(warp_inst_t &inst, unsigned lane_id) {
dim3 tid = get_tid();
printf(
"%u [thd=%u][i=%u] : ctaid=(%u,%u,%u) tid=(%u,%u,%u) icount=%u "
- "[pc=%u] (%s:%u - %s) [0x%llx]\n",
+ "[pc=%llu] (%s:%u - %s) [0x%llx]\n",
m_gpu->gpgpu_ctx->func_sim->g_ptx_sim_num_insn, get_uid(), pI->uid(),
ctaid.x, ctaid.y, ctaid.z, tid.x, tid.y, tid.z, get_icount(), pc,
pI->source_file(), pI->source_line(), pI->get_source(),
@@ -2376,7 +2380,7 @@ void cuda_sim::read_sim_environment_variables() {
"%s\n",
dbg_pc);
fflush(stdout);
- sscanf(dbg_pc, "%d", &g_debug_pc);
+ sscanf(dbg_pc, "%llu", &g_debug_pc);
}
#if CUDART_VERSION > 1010
diff --git a/src/cuda-sim/cuda_device_runtime.cc b/src/cuda-sim/cuda_device_runtime.cc
index 4a99c1c..8ed90bc 100644
--- a/src/cuda-sim/cuda_device_runtime.cc
+++ b/src/cuda-sim/cuda_device_runtime.cc
@@ -36,7 +36,7 @@ void cuda_device_runtime::gpgpusim_cuda_getParameterBufferV2(
unsigned n_args = target_func->num_args();
assert(n_args == 4);
- function_info *child_kernel_entry;
+ function_info *child_kernel_entry = NULL;
struct dim3 grid_dim, block_dim;
unsigned int shared_mem;
@@ -258,7 +258,7 @@ void cuda_device_runtime::gpgpusim_cuda_streamCreateWithFlags(
assert(n_args == 2);
size_t generic_pStream_addr;
- addr_t pStream_addr;
+ addr_t pStream_addr = 0;
unsigned int flags;
for (unsigned arg = 0; arg < n_args; arg++) {
const operand_info &actual_param_op =
diff --git a/src/cuda-sim/memory.cc b/src/cuda-sim/memory.cc
index 1323837..036bada 100644
--- a/src/cuda-sim/memory.cc
+++ b/src/cuda-sim/memory.cc
@@ -109,11 +109,11 @@ void memory_space_impl<BSIZE>::read_single_block(mem_addr_t blk_idx,
if ((addr + length) > (blk_idx + 1) * BSIZE) {
printf(
"GPGPU-Sim PTX: ERROR * access to memory \'%s\' is unaligned : "
- "addr=0x%x, length=%zu\n",
+ "addr=0x%llx, length=%zu\n",
m_name.c_str(), addr, length);
printf(
- "GPGPU-Sim PTX: (addr+length)=0x%lx > 0x%x=(index+1)*BSIZE, "
- "index=0x%x, BSIZE=0x%x\n",
+ "GPGPU-Sim PTX: (addr+length)=0x%llx > 0x%llx=(index+1)*BSIZE, "
+ "index=0x%llx, BSIZE=0x%x\n",
(addr + length), (blk_idx + 1) * BSIZE, blk_idx, BSIZE);
throw 1;
}
@@ -169,7 +169,7 @@ void memory_space_impl<BSIZE>::print(const char *format, FILE *fout) const {
typename map_t::const_iterator i_page;
for (i_page = m_data.begin(); i_page != m_data.end(); ++i_page) {
- fprintf(fout, "%s %08x:", m_name.c_str(), i_page->first);
+ fprintf(fout, "%s %08llx:", m_name.c_str(), i_page->first);
i_page->second.print(format, fout);
}
}
diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc
index 029cf73..f25f1d5 100644
--- a/src/cuda-sim/ptx_ir.cc
+++ b/src/cuda-sim/ptx_ir.cc
@@ -1470,7 +1470,7 @@ std::string ptx_instruction::to_string() const {
unsigned used_bytes = 0;
if (!is_label()) {
used_bytes +=
- snprintf(buf + used_bytes, STR_SIZE - used_bytes, " PC=0x%03x ", m_PC);
+ snprintf(buf + used_bytes, STR_SIZE - used_bytes, " PC=0x%03llx ", m_PC);
} else {
used_bytes +=
snprintf(buf + used_bytes, STR_SIZE - used_bytes, " ");
diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc
index 4e91763..df35498 100644
--- a/src/cuda-sim/ptx_loader.cc
+++ b/src/cuda-sim/ptx_loader.cc
@@ -95,7 +95,7 @@ void gpgpu_context::print_ptx_file(const char *p, unsigned source_num,
const ptx_instruction *pI = ptx_parser->ptx_instruction_lookup(filename, n);
char pc[64];
if (pI && pI->get_PC())
- snprintf(pc, 64, "%4u", pI->get_PC());
+ snprintf(pc, 64, "%4llu", pI->get_PC());
else
snprintf(pc, 64, " ");
printf(" _%u.ptx %4u (pc=%s): %s\n", source_num, n, pc, t);
@@ -240,7 +240,7 @@ void fix_duplicate_errors(char fname2[1024]) {
unsigned oldlinenum = 1;
unsigned linenum;
char *startptr = ptxdata;
- char *funcptr;
+ char *funcptr = NULL;
char *tempptr = ptxdata - 1;
char *lineptr = ptxdata - 1;
@@ -320,7 +320,7 @@ void fix_duplicate_errors(char fname2[1024]) {
// we need the application name here too.
char *get_app_binary_name() {
char exe_path[1025];
- char *self_exe_path;
+ char *self_exe_path = NULL;
#ifdef __APPLE__
// AMRUTH: get apple device and check the result.
printf("WARNING: not tested for Apple-mac devices \n");
diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc
index 86a33c2..a80eeae 100644
--- a/src/cuda-sim/ptx_parser.cc
+++ b/src/cuda-sim/ptx_parser.cc
@@ -206,7 +206,7 @@ void ptx_recognizer::end_function() {
gpgpu_ptx_assemble(g_func_info->get_name(), g_func_info);
g_current_symbol_table = g_global_symbol_table;
- PTX_PARSE_DPRINTF("function %s, PC = %d\n", g_func_info->get_name().c_str(),
+ PTX_PARSE_DPRINTF("function %s, PC = %llu\n", g_func_info->get_name().c_str(),
g_func_info->get_start_PC());
}
@@ -486,7 +486,7 @@ void ptx_recognizer::add_identifier(const char *identifier, int array_dim,
case param_space_local:
printf(
"GPGPU-Sim PTX: allocating stack frame region for .param \"%s\" from "
- "0x%x to 0x%lx\n",
+ "0x%llx to 0x%llx\n",
identifier, g_current_symbol_table->get_local_next(),
g_current_symbol_table->get_local_next() + num_bits / 8);
fflush(stdout);
@@ -521,7 +521,7 @@ void ptx_recognizer::add_constptr(const char *identifier1,
unsigned addr = s2->get_address();
- printf("GPGPU-Sim PTX: moving \"%s\" from 0x%x to 0x%x (%s+%x)\n",
+ printf("GPGPU-Sim PTX: moving \"%s\" from 0x%llx to 0x%x (%s+%d)\n",
identifier1, s1->get_address(), addr + offset, identifier2, offset);
s1->set_address(addr + offset);
diff --git a/src/cuda-sim/ptx_sim.cc b/src/cuda-sim/ptx_sim.cc
index dc801f8..6503499 100644
--- a/src/cuda-sim/ptx_sim.cc
+++ b/src/cuda-sim/ptx_sim.cc
@@ -369,7 +369,7 @@ static void print_reg(FILE *fp, std::string name, ptx_reg_t value,
fprintf(fp, ".u64 %llu [0x%llx]\n", value.u64, value.u64);
break;
case F16_TYPE:
- fprintf(fp, ".f16 %f [0x%04x]\n", value.f16, (unsigned)value.u16);
+ fprintf(fp, ".f16 %f [0x%04x]\n", static_cast<float>(value.f16), (unsigned)value.u16);
break;
case F32_TYPE:
fprintf(fp, ".f32 %.15lf [0x%08x]\n", value.f32, value.u32);
diff --git a/src/debug.cc b/src/debug.cc
index 29506bd..e23ffd4 100644
--- a/src/debug.cc
+++ b/src/debug.cc
@@ -124,7 +124,7 @@ void gpgpu_sim::gpgpu_debug() {
fflush(stdout);
char line[1024];
- fgets(line, 1024, stdin);
+ char * ptr = fgets(line, 1024, stdin);
char *tok = strtok(line, " \t\n");
if (!strcmp(tok, "dp")) {
@@ -136,7 +136,11 @@ void gpgpu_sim::gpgpu_debug() {
fflush(stdout);
} else if (!strcmp(tok, "q") || !strcmp(tok, "quit")) {
printf("\nreally quit GPGPU-Sim (y/n)?\n");
- fgets(line, 1024, stdin);
+ ptr = fgets(line, 1024, stdin);
+ if(ptr == NULL ){
+ printf("can't read input\n");
+ exit(0);
+ }
tok = strtok(line, " \t\n");
if (!strcmp(tok, "y")) {
exit(0);
diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc
index 19714ec..f4f83f9 100644
--- a/src/gpgpu-sim/addrdec.cc
+++ b/src/gpgpu-sim/addrdec.cc
@@ -519,7 +519,7 @@ void linear_to_raw_address_translation::sweep_test() const {
h->second, raw_addr);
abort();
} else {
- assert((int)tlx.chip < m_n_channel);
+ assert(tlx.chip < m_n_channel);
// ensure that partition_address() returns the concatenated address
if ((ADDR_CHIP_S != -1 and raw_addr >= (1ULL << ADDR_CHIP_S)) or
(ADDR_CHIP_S == -1 and raw_addr >= (1ULL << addrdec_mklow[CHIP]))) {
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index 4bbf7e2..aa693b5 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -563,10 +563,12 @@ class cache_config {
char ct, rp, wp, ap, mshr_type, wap, sif;
int ntok =
- sscanf(config, "%c:%u:%u:%u,%c:%c:%c:%c:%c,%c:%u:%u,%u:%u,%u", &ct,
- &m_nset, &m_line_sz, &m_assoc, &rp, &wp, &ap, &wap, &sif,
- &mshr_type, &m_mshr_entries, &m_mshr_max_merge,
- &m_miss_queue_size, &m_result_fifo_entries, &m_data_port_width);
+ sscanf(config, "%c:%u:%u:%u,%c:%c:%c:%c:%c,%c:%u:%u,%u:%u,%u",
+ &ct, &m_nset, &m_line_sz, &m_assoc,
+ &rp, &wp, &ap, &wap, &sif,
+ &mshr_type, &m_mshr_entries, &m_mshr_max_merge,
+ &m_miss_queue_size, &m_result_fifo_entries,
+ &m_data_port_width);
if (ntok < 12) {
if (!strcmp(config, "none")) {
@@ -721,9 +723,17 @@ class cache_config {
"Invalid cache configuration: FETCH_ON_WRITE and LAZY_FETCH_ON_READ "
"cannot work properly with ON_FILL policy. Cache must be ON_MISS. ");
}
+
if (m_cache_type == SECTOR) {
- assert(m_line_sz / SECTOR_SIZE == SECTOR_CHUNCK_SIZE &&
- m_line_sz % SECTOR_SIZE == 0);
+ bool cond =
+ m_line_sz / SECTOR_SIZE == SECTOR_CHUNCK_SIZE &&
+ m_line_sz % SECTOR_SIZE == 0;
+ if(!cond){
+ std::cerr<<"error: For sector cache, the simulator uses hard-coded "
+ "SECTOR_SIZE and SECTOR_CHUNCK_SIZE. The line size "
+ "must be product of both values.\n";
+ assert(0);
+ }
}
// default: port to data array width and granularity = line size
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 5af244b..ea50fa0 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -586,26 +586,26 @@ void shader_core_config::reg_options(class OptionParser *opp) {
"ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_"
"INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE",
"1,1,1,1,1,1,1,1,1,1,1,1,1");
- option_parser_register(opp, "-gpgpu_tensor_core_avail", OPT_INT32,
+ option_parser_register(opp, "-gpgpu_tensor_core_avail", OPT_UINT32,
&gpgpu_tensor_core_avail,
"Tensor Core Available (default=0)", "0");
- option_parser_register(opp, "-gpgpu_num_sp_units", OPT_INT32,
+ option_parser_register(opp, "-gpgpu_num_sp_units", OPT_UINT32,
&gpgpu_num_sp_units, "Number of SP units (default=1)",
"1");
- option_parser_register(opp, "-gpgpu_num_dp_units", OPT_INT32,
+ option_parser_register(opp, "-gpgpu_num_dp_units", OPT_UINT32,
&gpgpu_num_dp_units, "Number of DP units (default=0)",
"0");
- option_parser_register(opp, "-gpgpu_num_int_units", OPT_INT32,
+ option_parser_register(opp, "-gpgpu_num_int_units", OPT_UINT32,
&gpgpu_num_int_units,
"Number of INT units (default=0)", "0");
- option_parser_register(opp, "-gpgpu_num_sfu_units", OPT_INT32,
+ option_parser_register(opp, "-gpgpu_num_sfu_units", OPT_UINT32,
&gpgpu_num_sfu_units, "Number of SF units (default=1)",
"1");
- option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_INT32,
+ option_parser_register(opp, "-gpgpu_num_tensor_core_units", OPT_UINT32,
&gpgpu_num_tensor_core_units,
"Number of tensor_core units (default=1)", "0");
option_parser_register(
- opp, "-gpgpu_num_mem_units", OPT_INT32, &gpgpu_num_mem_units,
+ opp, "-gpgpu_num_mem_units", OPT_UINT32, &gpgpu_num_mem_units,
"Number if ldst units (default=1) WARNING: not hooked up to anything",
"1");
option_parser_register(
@@ -2053,7 +2053,7 @@ void gpgpu_sim::cycle() {
m_cluster[i]->get_current_occupancy(active, total);
}
DPRINTFG(LIVENESS,
- "uArch: inst.: %lld (ipc=%4.1f, occ=%0.4f\% [%llu / %llu]) "
+ "uArch: inst.: %lld (ipc=%4.1f, occ=%0.4f%% [%llu / %llu]) "
"sim_rate=%u (inst/sec) elapsed = %u:%u:%02u:%02u / %s",
gpu_tot_sim_insn + gpu_sim_insn,
(double)gpu_sim_insn / (double)gpu_sim_cycle,
diff --git a/src/gpgpu-sim/local_interconnect.cc b/src/gpgpu-sim/local_interconnect.cc
index 0e20462..df6bd7b 100644
--- a/src/gpgpu-sim/local_interconnect.cc
+++ b/src/gpgpu-sim/local_interconnect.cc
@@ -159,8 +159,8 @@ void xbar_router::RR_Advance() {
}
if (verbose) {
- printf("%d : cycle %d : conflicts = %d\n", m_id, cycles, conflict_sub);
- printf("%d : cycle %d : passing reqs = %d\n", m_id, cycles, reqs);
+ printf("%d : cycle %llu : conflicts = %d\n", m_id, cycles, conflict_sub);
+ printf("%d : cycle %llu : passing reqs = %d\n", m_id, cycles, reqs);
}
// collect some stats about buffer util
@@ -217,7 +217,7 @@ void xbar_router::iSLIP_Advance() {
out_buffers[_packet.output_deviceID].push(_packet);
in_buffers[node_id].pop();
if (verbose)
- printf("%d : cycle %d : send req from %d to %d\n", m_id, cycles,
+ printf("%d : cycle %llu : send req from %d to %d\n", m_id, cycles,
node_id, i - _n_shader);
if (grant_cycles_count == 1)
next_node[i] = (++node_id % total_nodes);
@@ -228,7 +228,7 @@ void xbar_router::iSLIP_Advance() {
Packet _packet2 = in_buffers[node_id2].front();
if (_packet2.output_deviceID == i)
- printf("%d : cycle %d : cannot send req from %d to %d\n",
+ printf("%d : cycle %llu : cannot send req from %d to %d\n",
m_id, cycles, node_id2, i - _n_shader);
}
}
@@ -248,7 +248,7 @@ void xbar_router::iSLIP_Advance() {
}
if (verbose)
- printf("%d : cycle %d : grant_cycles = %d\n", m_id, cycles, grant_cycles);
+ printf("%d : cycle %llu : grant_cycles = %d\n", m_id, cycles, grant_cycles);
if (active && grant_cycles_count == 1)
grant_cycles_count = grant_cycles;
@@ -256,8 +256,8 @@ void xbar_router::iSLIP_Advance() {
grant_cycles_count--;
if (verbose) {
- printf("%d : cycle %d : conflicts = %d\n", m_id, cycles, conflict_sub);
- printf("%d : cycle %d : passing reqs = %d\n", m_id, cycles, reqs);
+ printf("%d : cycle %llu : conflicts = %d\n", m_id, cycles, conflict_sub);
+ printf("%d : cycle %llu : passing reqs = %d\n", m_id, cycles, reqs);
}
// collect some stats about buffer util
diff --git a/src/gpgpu-sim/power_interface.cc b/src/gpgpu-sim/power_interface.cc
index 470f2f9..45a09bc 100644
--- a/src/gpgpu-sim/power_interface.cc
+++ b/src/gpgpu-sim/power_interface.cc
@@ -269,7 +269,7 @@ void calculate_hw_mcpat(const gpgpu_sim_config &config,
if((power_simulation_mode == 2) && (accelwattch_hybrid_configuration[HW_L1_WM]))
l1_write_misses = power_stats->get_l1d_write_misses(1) - power_stats->l1w_misses_kernel;
- if(aggregate_power_stats){
+ if(aggregate_power_stats){
power_stats->tot_inst_execution += power_stats->get_total_inst(1);
power_stats->tot_int_inst_execution += power_stats->get_total_int_inst(1);
power_stats->tot_fp_inst_execution += power_stats->get_total_fp_inst(1);
@@ -281,16 +281,16 @@ void calculate_hw_mcpat(const gpgpu_sim_config &config,
l1_read_hits + l1_read_misses,
l1_write_hits + l1_write_misses,
power_stats->commited_inst_execution);
- }
- else{
- wrapper->set_inst_power(
+ }
+ else{
+ wrapper->set_inst_power(
shdr_config->gpgpu_clock_gated_lanes, cycle, //TODO: core.[0] cycles counts don't matter, remove this
cycle, power_stats->get_total_inst(1),
power_stats->get_total_int_inst(1), power_stats->get_total_fp_inst(1),
l1_read_hits + l1_read_misses,
l1_write_hits + l1_write_misses,
power_stats->get_committed_inst(1));
- }
+ }
// Single RF for both int and fp ops -- activity factor set to 0 for Accelwattch HW and Accelwattch Hybrid because no HW Perf Stats for register files
wrapper->set_regfile_power(power_stats->get_regfile_reads(1),
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index a9732d8..69992f7 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -107,7 +107,7 @@ void shader_core_ctx::create_front_pipeline() {
m_pipeline_reg.push_back(
register_set(m_config->pipe_widths[j], pipeline_stage_name_decode[j]));
}
- for (int j = 0; j < m_config->m_specialized_unit.size(); j++) {
+ for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) {
m_pipeline_reg.push_back(
register_set(m_config->m_specialized_unit[j].id_oc_spec_reg_width,
m_config->m_specialized_unit[j].name));
@@ -115,7 +115,7 @@ void shader_core_ctx::create_front_pipeline() {
m_specilized_dispatch_reg.push_back(
&m_pipeline_reg[m_pipeline_reg.size() - 1]);
}
- for (int j = 0; j < m_config->m_specialized_unit.size(); j++) {
+ for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) {
m_pipeline_reg.push_back(
register_set(m_config->m_specialized_unit[j].oc_ex_spec_reg_width,
m_config->m_specialized_unit[j].name));
@@ -140,7 +140,7 @@ void shader_core_ctx::create_front_pipeline() {
if (m_config->gpgpu_num_int_units > 0)
assert(m_config->gpgpu_num_sched_per_core ==
m_pipeline_reg[ID_OC_INT].get_size());
- for (int j = 0; j < m_config->m_specialized_unit.size(); j++) {
+ for (unsigned j = 0; j < m_config->m_specialized_unit.size(); j++) {
if (m_config->m_specialized_unit[j].num_units > 0)
assert(m_config->gpgpu_num_sched_per_core ==
m_config->m_specialized_unit[j].id_oc_spec_reg_width);
@@ -1645,7 +1645,7 @@ void swl_scheduler::order_warps() {
}
void shader_core_ctx::read_operands() {
- for (int i = 0; i < m_config->reg_file_port_throughput; ++i)
+ for (unsigned int i = 0; i < m_config->reg_file_port_throughput; ++i)
m_operand_collector.step();
}
@@ -1949,7 +1949,7 @@ mem_stage_stall_type ldst_unit::process_memory_access_queue_l1cache(
if (inst.accessq_empty()) return result;
if (m_config->m_L1D_config.l1_latency > 0) {
- for (int j = 0; j < m_config->m_L1D_config.l1_banks;
+ for (unsigned int j = 0; j < m_config->m_L1D_config.l1_banks;
j++) { // We can handle at max l1_banks reqs per cycle
if (inst.accessq_empty()) return result;
@@ -2003,7 +2003,7 @@ mem_stage_stall_type ldst_unit::process_memory_access_queue_l1cache(
}
void ldst_unit::L1_latency_queue_cycle() {
- for (int j = 0; j < m_config->m_L1D_config.l1_banks; j++) {
+ for (unsigned int j = 0; j < m_config->m_L1D_config.l1_banks; j++) {
if ((l1_latency_queue[j][0]) != NULL) {
mem_fetch *mf_next = l1_latency_queue[j][0];
std::list<cache_event> events;
@@ -2330,7 +2330,7 @@ sp_unit::sp_unit(register_set *result_port, const shader_core_config *config,
specialized_unit::specialized_unit(register_set *result_port,
const shader_core_config *config,
- shader_core_ctx *core, unsigned supported_op,
+ shader_core_ctx *core, int supported_op,
char *unit_name, unsigned latency,
unsigned issue_reg_id)
: pipelined_simd_unit(result_port, config, latency, core, issue_reg_id) {
@@ -3084,7 +3084,7 @@ void warp_inst_t::print(FILE *fout) const {
fprintf(fout, "bubble\n");
return;
} else
- fprintf(fout, "0x%04x ", pc);
+ fprintf(fout, "0x%04llx ", pc);
fprintf(fout, "w%02d[", m_warp_id);
for (unsigned j = 0; j < m_config->warp_size; j++)
fprintf(fout, "%c", (active(j) ? '1' : '0'));
@@ -3270,7 +3270,7 @@ void shader_core_ctx::display_pipeline(FILE *fout, int print_mem,
if (!m_inst_fetch_buffer.m_valid)
fprintf(fout, "bubble\n");
else {
- fprintf(fout, "w%2u : pc = 0x%x, nbytes = %u\n",
+ fprintf(fout, "w%2u : pc = 0x%llx, nbytes = %u\n",
m_inst_fetch_buffer.m_warp_id, m_inst_fetch_buffer.m_pc,
m_inst_fetch_buffer.m_nbytes);
}
@@ -3503,7 +3503,7 @@ void shader_core_ctx::cycle() {
execute();
read_operands();
issue();
- for (int i = 0; i < m_config->inst_fetch_throughput; ++i) {
+ for (unsigned int i = 0; i < m_config->inst_fetch_throughput; ++i) {
decode();
fetch();
}
@@ -3936,7 +3936,7 @@ bool shd_warp_t::waiting() {
void shd_warp_t::print(FILE *fout) const {
if (!done_exit()) {
- fprintf(fout, "w%02u npc: 0x%04x, done:%c%c%c%c:%2u i:%u s:%u a:%u (done: ",
+ fprintf(fout, "w%02u npc: 0x%04llx, done:%c%c%c%c:%2u i:%u s:%u a:%u (done: ",
m_warp_id, m_next_pc, (functional_done() ? 'f' : ' '),
(stores_done() ? 's' : ' '), (inst_in_pipeline() ? ' ' : 'i'),
(done_exit() ? 'e' : ' '), n_completed, m_inst_in_pipeline,
@@ -4012,7 +4012,7 @@ void opndcoll_rfu_t::init(unsigned num_banks, shader_core_ctx *shader) {
sub_core_model = shader->get_config()->sub_core_model;
m_num_warp_scheds = shader->get_config()->gpgpu_num_sched_per_core;
- unsigned reg_id;
+ unsigned reg_id = 0;
if (sub_core_model) {
assert(num_banks % shader->get_config()->gpgpu_num_sched_per_core == 0);
assert(m_num_warp_scheds <= m_cu.size() &&
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 986105e..9243077 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1284,7 +1284,7 @@ class sp_unit : public pipelined_simd_unit {
class specialized_unit : public pipelined_simd_unit {
public:
specialized_unit(register_set *result_port, const shader_core_config *config,
- shader_core_ctx *core, unsigned supported_op,
+ shader_core_ctx *core, int supported_op,
char *unit_name, unsigned latency, unsigned issue_reg_id);
virtual bool can_issue(const warp_inst_t &inst) const {
if (inst.op != m_supported_op) {
@@ -1297,7 +1297,7 @@ class specialized_unit : public pipelined_simd_unit {
bool is_issue_partitioned() { return true; }
private:
- unsigned m_supported_op;
+ int m_supported_op;
};
class simt_core_cluster;
@@ -1622,13 +1622,13 @@ class shader_core_config : public core_config {
unsigned int gpgpu_operand_collector_num_out_ports_gen;
unsigned int gpgpu_operand_collector_num_out_ports_int;
- int gpgpu_num_sp_units;
- int gpgpu_tensor_core_avail;
- int gpgpu_num_dp_units;
- int gpgpu_num_sfu_units;
- int gpgpu_num_tensor_core_units;
- int gpgpu_num_mem_units;
- int gpgpu_num_int_units;
+ unsigned int gpgpu_num_sp_units;
+ unsigned int gpgpu_tensor_core_avail;
+ unsigned int gpgpu_num_dp_units;
+ unsigned int gpgpu_num_sfu_units;
+ unsigned int gpgpu_num_tensor_core_units;
+ unsigned int gpgpu_num_mem_units;
+ unsigned int gpgpu_num_int_units;
// Shader core resources
unsigned gpgpu_shader_registers;
diff --git a/src/gpgpu-sim/stat-tool.cc b/src/gpgpu-sim/stat-tool.cc
index 0513d17..08bbe9e 100644
--- a/src/gpgpu-sim/stat-tool.cc
+++ b/src/gpgpu-sim/stat-tool.cc
@@ -519,7 +519,7 @@ void thread_insn_span::print_span(FILE *fout) const {
fprintf(fout, "%d: ", (int)m_cycle);
span_count_map::const_iterator i_sc = m_insn_span_count.begin();
for (; i_sc != m_insn_span_count.end(); ++i_sc) {
- fprintf(fout, "%d ", i_sc->first);
+ fprintf(fout, "%llx ", i_sc->first);
}
fprintf(fout, "\n");
}
diff --git a/src/intersim2/networks/anynet.cpp b/src/intersim2/networks/anynet.cpp
index 4db1dfb..d7c6f22 100644
--- a/src/intersim2/networks/anynet.cpp
+++ b/src/intersim2/networks/anynet.cpp
@@ -491,7 +491,7 @@ void AnyNet::readFile(){
}
sort(node_check.begin(), node_check.end());
for(size_t i = 0; i<node_check.size(); i++){
- if(node_check[i] != i){
+ if(node_check[i] != (int)i){
cout<<"Anynet:booksim trafficmanager assumes sequential node numbering starting at 0\n";
assert(false);
}
diff --git a/src/intersim2/networks/kncube.cpp b/src/intersim2/networks/kncube.cpp
index 03e13e7..178c905 100644
--- a/src/intersim2/networks/kncube.cpp
+++ b/src/intersim2/networks/kncube.cpp
@@ -231,7 +231,7 @@ void KNCube::InsertRandomFaults( const Configuration &config )
int num_fails;
unsigned long prev_seed;
- int node, chan;
+ int node, chan = 0;
int i, j, t, n, c;
bool available;
diff --git a/src/intersim2/networks/qtree.cpp b/src/intersim2/networks/qtree.cpp
index 7214947..37d3d7c 100644
--- a/src/intersim2/networks/qtree.cpp
+++ b/src/intersim2/networks/qtree.cpp
@@ -84,7 +84,7 @@ void QTree::_BuildNet( const Configuration& config )
{
ostringstream routerName;
- int h, r, pos, port;
+ int h, r = 0 , pos, port;
for (h = 0; h < _n; h++) {
for (pos = 0 ; pos < powi( _k, h ) ; ++pos ) {
diff --git a/src/intersim2/vc.cpp b/src/intersim2/vc.cpp
index 94e8c6b..4c94445 100644
--- a/src/intersim2/vc.cpp
+++ b/src/intersim2/vc.cpp
@@ -82,7 +82,7 @@ void VC::AddFlit( Flit *f )
assert(f);
if(_expected_pid >= 0) {
- if(f->pid != _expected_pid) {
+ if((long long int)f->pid != _expected_pid) {
ostringstream err;
err << "Received flit " << f->id << " with unexpected packet ID: " << f->pid
<< " (expected: " << _expected_pid << ")";
diff --git a/src/stream_manager.h b/src/stream_manager.h
index afcbb0e..561f54b 100644
--- a/src/stream_manager.h
+++ b/src/stream_manager.h
@@ -73,7 +73,7 @@ struct CUevent_st {
int m_uid;
bool m_blocking;
bool m_done;
- int m_updates;
+ unsigned int m_updates;
unsigned int m_issued;
time_t m_wallclock;
double m_gpu_tot_sim_cycle;
generated by cgit v1.3 (git 2.53.0) at 2026-07-10 23:27:09 +0000