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-rw-r--r--src/cuda-sim/cuda-sim.cc3
-rw-r--r--src/cuda-sim/ptx_ir.cc9
-rw-r--r--src/cuda-sim/ptx_ir.h2
-rw-r--r--src/gpgpu-sim/gpu-sim.cc4
-rw-r--r--src/gpgpu-sim/gpu-sim.h1
-rw-r--r--src/gpgpu-sim/l2cache.cc33
-rw-r--r--src/gpgpu-sim/l2cache.h2
-rw-r--r--src/gpgpu-sim/shader.cc19
-rw-r--r--src/gpgpu-sim/shader.h6
9 files changed, 43 insertions, 36 deletions
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 1967b2f..1982218 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -427,6 +427,7 @@ void gpgpu_t::gpu_memset( size_t dst_start_addr, int c, size_t count )
void ptx_print_insn( address_type pc, FILE *fp )
{
+ static unsigned size=1;
std::map<unsigned,function_info*>::iterator f = g_pc_to_finfo.find(pc);
if( f == g_pc_to_finfo.end() ) {
fprintf(fp,"<no instruction at address 0x%x>", pc );
@@ -434,7 +435,7 @@ void ptx_print_insn( address_type pc, FILE *fp )
}
function_info *finfo = f->second;
assert( finfo );
- finfo->print_insn(pc,fp);
+ size = finfo->print_insn(pc,fp);
}
void ptx_instruction::set_opcode_and_latency()
diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc
index 50167b8..b98e774 100644
--- a/src/cuda-sim/ptx_ir.cc
+++ b/src/cuda-sim/ptx_ir.cc
@@ -1193,8 +1193,9 @@ function_info::function_info(int entry_point )
m_local_mem_framesize = 0;
}
-void function_info::print_insn( unsigned pc, FILE * fp ) const
+unsigned function_info::print_insn( unsigned pc, FILE * fp ) const
{
+ unsigned inst_size=1; // return offset to next instruction or 1 if unknown
unsigned index = pc - m_start_PC;
char command[1024];
char buffer[1024];
@@ -1206,11 +1207,13 @@ void function_info::print_insn( unsigned pc, FILE * fp ) const
if ( index >= m_instr_mem_size ) {
fprintf(fp, "<past last instruction (max pc=%u)>", m_start_PC + m_instr_mem_size - 1 );
} else {
- if ( m_instr_mem[index] != NULL )
+ if ( m_instr_mem[index] != NULL ) {
m_instr_mem[index]->print_insn(fp);
- else
+ inst_size = m_instr_mem[index]->isize;
+ } else
fprintf(fp, "<no instruction at pc = %u>", pc );
}
+ return inst_size;
}
void gpgpu_ptx_assemble( std::string kname, void *kinfo )
diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h
index 3d65712..71940ab 100644
--- a/src/cuda-sim/ptx_ir.h
+++ b/src/cuda-sim/ptx_ir.h
@@ -1060,7 +1060,7 @@ public:
{
return m_name;
}
- void print_insn( unsigned pc, FILE * fp ) const;
+ unsigned print_insn( unsigned pc, FILE * fp ) const;
void add_inst( const std::list<ptx_instruction*> &instructions )
{
m_instructions = instructions;
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 8c1be87..dbae72c 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -749,7 +749,7 @@ void gpgpu_sim::cycle()
// L2 operations follow L2 clock domain
if (clock_mask & L2) {
for (unsigned i=0;i<m_memory_config->m_n_mem;i++)
- m_memory_partition_unit[i]->cache_cycle();
+ m_memory_partition_unit[i]->cache_cycle(gpu_sim_cycle+gpu_tot_sim_cycle);
}
if (clock_mask & ICNT) {
@@ -885,7 +885,7 @@ void gpgpu_sim::dump_pipeline( int mask, int s, int m ) const
if(s != -1) {
i = s;
}
- if(mask&1) m_cluster[sid_to_cluster(i)]->display_pipeline(i,stdout,1,mask & 0x2E);
+ if(mask&1) m_cluster[m_shader_config->sid_to_cluster(i)]->display_pipeline(i,stdout,1,mask & 0x2E);
if(s != -1) {
break;
}
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index 903eb3c..54b32d0 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -286,7 +286,6 @@ private:
void print_shader_cycle_distro( FILE *fout ) const;
void gpgpu_debug();
- unsigned sid_to_cluster( unsigned sid ) const;
///// data /////
diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc
index fa55d0b..14f1f12 100644
--- a/src/gpgpu-sim/l2cache.cc
+++ b/src/gpgpu-sim/l2cache.cc
@@ -120,7 +120,7 @@ memory_partition_unit::~memory_partition_unit()
delete m_L2interface;
}
-void memory_partition_unit::cache_cycle()
+void memory_partition_unit::cache_cycle( unsigned cycle )
{
// L2 fill responses
if ( m_L2cache->access_ready() && !m_L2_icnt_queue->full() ) {
@@ -172,6 +172,14 @@ void memory_partition_unit::cache_cycle()
m_icnt_L2_queue->pop();
}
}
+
+ // ROP delay queue
+ if( !m_rop.empty() && (cycle >= m_rop.front().ready_cycle) && !m_icnt_L2_queue->full() ) {
+ mem_fetch* mf = m_rop.front().req;
+ m_rop.pop();
+ m_icnt_L2_queue->push(mf);
+ mf->set_status(IN_PARTITION_ICNT_TO_L2_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
+ }
}
bool memory_partition_unit::full() const
@@ -231,18 +239,17 @@ void memory_partition_unit::push( mem_fetch* req, unsigned long long cycle )
{
if (req) {
m_request_tracker.insert(req);
- rop_delay_t r;
- r.req = req;
- r.ready_cycle = cycle + 115; // Add 115*4=460 delay cycles
- m_rop.push(r);
- req->set_status(IN_PARTITION_ROP_DELAY,gpu_sim_cycle+gpu_tot_sim_cycle);
- }
- if ( !m_rop.empty() && (cycle >= m_rop.front().ready_cycle) ) {
- mem_fetch* mf = m_rop.front().req;
- m_rop.pop();
- m_stats->memlatstat_icnt2mem_pop(mf);
- m_icnt_L2_queue->push(mf);
- mf->set_status(IN_PARTITION_ICNT_TO_L2_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
+ m_stats->memlatstat_icnt2mem_pop(req);
+ if( req->istexture() ) {
+ m_icnt_L2_queue->push(req);
+ req->set_status(IN_PARTITION_ICNT_TO_L2_QUEUE,gpu_sim_cycle+gpu_tot_sim_cycle);
+ } else {
+ rop_delay_t r;
+ r.req = req;
+ r.ready_cycle = cycle + 115; // Add 115*4=460 delay cycles
+ m_rop.push(r);
+ req->set_status(IN_PARTITION_ROP_DELAY,gpu_sim_cycle+gpu_tot_sim_cycle);
+ }
}
}
diff --git a/src/gpgpu-sim/l2cache.h b/src/gpgpu-sim/l2cache.h
index b80f384..b7ab49e 100644
--- a/src/gpgpu-sim/l2cache.h
+++ b/src/gpgpu-sim/l2cache.h
@@ -82,7 +82,7 @@ public:
bool busy() const;
- void cache_cycle();
+ void cache_cycle( unsigned cycle );
void dram_cycle();
bool full() const;
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index f723b78..692eace 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -309,14 +309,9 @@ void pdom_warp_ctx_t::pdom_update_warp_mask()
assert(scheduled_warp->m_stack_top < m_warp_size * 2);
}
-unsigned gpgpu_sim::sid_to_cluster( unsigned sid ) const
-{
- return sid / m_shader_config->n_simt_cores_per_cluster;
-}
-
void gpgpu_sim::get_pdom_stack_top_info( unsigned sid, unsigned tid, unsigned *pc, unsigned *rpc )
{
- unsigned cluster_id = sid_to_cluster(sid);
+ unsigned cluster_id = m_shader_config->sid_to_cluster(sid);
m_cluster[cluster_id]->get_pdom_stack_top_info(sid,tid,pc,rpc);
}
@@ -2002,8 +1997,10 @@ simt_core_cluster::simt_core_cluster( class gpgpu_sim *gpu,
m_gpu = gpu;
m_stats = stats;
m_core = new shader_core_ctx*[ config->n_simt_cores_per_cluster ];
- for( unsigned i=0; i < config->n_simt_cores_per_cluster; i++ )
- m_core[i] = new shader_core_ctx(gpu,this,cid_to_sid(i),m_cluster_id,config,mem_config,stats);
+ for( unsigned i=0; i < config->n_simt_cores_per_cluster; i++ ) {
+ unsigned sid = m_config->cid_to_sid(i,m_cluster_id);
+ m_core[i] = new shader_core_ctx(gpu,this,sid,m_cluster_id,config,mem_config,stats);
+ }
}
void simt_core_cluster::core_cycle()
@@ -2095,7 +2092,7 @@ void simt_core_cluster::icnt_cycle()
{
if( !m_response_fifo.empty() ) {
mem_fetch *mf = m_response_fifo.front();
- unsigned cid = sid_to_cid(mf->get_sid());
+ unsigned cid = m_config->sid_to_cid(mf->get_sid());
if( mf->get_access_type() == INST_ACC_R ) {
// instruction fetch response
if( !m_core[cid]->fetch_unit_response_buffer_full() ) {
@@ -2124,11 +2121,11 @@ void simt_core_cluster::icnt_cycle()
void simt_core_cluster::get_pdom_stack_top_info( unsigned sid, unsigned tid, unsigned *pc, unsigned *rpc ) const
{
- unsigned cid = sid_to_cid(sid);
+ unsigned cid = m_config->sid_to_cid(sid);
m_core[cid]->get_pdom_stack_top_info(tid,pc,rpc);
}
void simt_core_cluster::display_pipeline( unsigned sid, FILE *fout, int print_mem, int mask )
{
- m_core[sid_to_cid(sid)]->display_pipeline(fout,print_mem,mask);
+ m_core[m_config->sid_to_cid(sid)]->display_pipeline(fout,print_mem,mask);
}
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index dd3d89e..52a7e35 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -936,6 +936,9 @@ struct shader_core_config : public core_config
void reg_options(class OptionParser * opp );
unsigned max_cta( const kernel_info_t &k ) const;
unsigned num_shader() const { return n_simt_clusters*n_simt_cores_per_cluster; }
+ unsigned sid_to_cluster( unsigned sid ) const { return sid / n_simt_cores_per_cluster; }
+ unsigned sid_to_cid( unsigned sid ) const { return sid % n_simt_cores_per_cluster; }
+ unsigned cid_to_sid( unsigned cid, unsigned cluster_id ) const { return cluster_id*n_simt_cores_per_cluster + cid; }
// data
char *gpgpu_shader_core_pipeline_opt;
@@ -1183,9 +1186,6 @@ public:
void display_pipeline( unsigned sid, FILE *fout, int print_mem, int mask );
private:
- unsigned sid_to_cid( unsigned sid ) const { return sid % m_config->n_simt_cores_per_cluster; }
- unsigned cid_to_sid( unsigned cid ) const { return m_cluster_id*m_config->n_simt_cores_per_cluster + cid; }
-
unsigned m_cluster_id;
gpgpu_sim *m_gpu;
const shader_core_config *m_config;
generated by cgit v1.3 (git 2.53.0) at 2026-07-10 23:35:03 +0000