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-rw-r--r--src/abstract_hardware_model.h2
-rw-r--r--src/gpgpu-sim/addrdec.cc2
-rw-r--r--src/gpgpu-sim/gpu-sim.cc51
-rw-r--r--src/gpgpu-sim/icnt_wrapper.cc12
-rw-r--r--src/gpgpu-sim/shader.cc2
-rw-r--r--src/gpgpu-sim/shader.h7
-rw-r--r--src/trace-driven/gpgpusim_trace_driven_main.cc3
-rw-r--r--src/trace-driven/kepler_opcode.h5
-rw-r--r--src/trace-driven/trace_driven.cc102
-rw-r--r--src/trace-driven/trace_driven.h28
10 files changed, 113 insertions, 101 deletions
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 135b03b..6c19e2d 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -70,7 +70,7 @@ enum FuncCache
enum AdaptiveCache
{
FIXED = 0,
- VOLTA = 1
+ ADAPTIVE_VOLTA = 1
};
#ifdef __cplusplus
diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc
index c34cb32..d430568 100644
--- a/src/gpgpu-sim/addrdec.cc
+++ b/src/gpgpu-sim/addrdec.cc
@@ -63,7 +63,7 @@ void linear_to_raw_address_translation::addrdec_setoption(option_parser_t opp)
option_parser_register(opp, "-gpgpu_mem_address_mask", OPT_INT32, &gpgpu_mem_address_mask,
"0 = old addressing mask, 1 = new addressing mask, 2 = new add. mask + flipped bank sel and chip sel bits",
"0");
- option_parser_register(opp, "-memory_partition_indexing", OPT_UINT32, &memory_partition_indexing,
+ option_parser_register(opp, "-gpgpu_memory_partition_indexing", OPT_UINT32, &memory_partition_indexing,
"0 = no indexing, 1 = bitwise xoring, 2 = IPoly, 3 = custom indexing",
"0");
}
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index cd5fa56..641ddbc 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -137,9 +137,9 @@ void power_config::reg_options(class OptionParser * opp)
void memory_config::reg_options(class OptionParser * opp)
{
- option_parser_register(opp, "-perf_sim_memcpy", OPT_BOOL, &m_perf_sim_memcpy,
+ option_parser_register(opp, "-gpgpu_perf_sim_memcpy", OPT_BOOL, &m_perf_sim_memcpy,
"Fill the L2 cache on memcpy", "1");
- option_parser_register(opp, "-simple_dram_model", OPT_BOOL, &simple_dram_model,
+ option_parser_register(opp, "-gpgpu_simple_dram_model", OPT_BOOL, &simple_dram_model,
"simple_dram_model with fixed latency and BW", "0");
option_parser_register(opp, "-gpgpu_dram_scheduler", OPT_INT32, &scheduler_type,
"0 = fifo, 1 = FR-FCFS (defaul)", "1");
@@ -187,13 +187,13 @@ void memory_config::reg_options(class OptionParser * opp)
option_parser_register(opp, "-gpgpu_dram_timing_opt", OPT_CSTR, &gpgpu_dram_timing_opt,
"DRAM timing parameters = {nbk:tCCD:tRRD:tRCD:tRAS:tRP:tRC:CL:WL:tCDLR:tWR:nbkgrp:tCCDL:tRTPL}",
"4:2:8:12:21:13:34:9:4:5:13:1:0:0");
- option_parser_register(opp, "-rop_latency", OPT_UINT32, &rop_latency,
+ option_parser_register(opp, "-gpgpu_l2_rop_latency", OPT_UINT32, &rop_latency,
"ROP queue latency (default 85)",
"85");
option_parser_register(opp, "-dram_latency", OPT_UINT32, &dram_latency,
"DRAM latency (default 30)",
"30");
- option_parser_register(opp, "-dual_bus_interface", OPT_UINT32, &dual_bus_interface,
+ option_parser_register(opp, "-dram_dual_bus_interface", OPT_UINT32, &dual_bus_interface,
"dual_bus_interface (default = 0) ",
"0");
option_parser_register(opp, "-dram_bnk_indexing_policy", OPT_UINT32, &dram_bnk_indexing_policy,
@@ -202,13 +202,13 @@ void memory_config::reg_options(class OptionParser * opp)
option_parser_register(opp, "-dram_bnkgrp_indexing_policy", OPT_UINT32, &dram_bnkgrp_indexing_policy,
"dram_bnkgrp_indexing_policy (0 = take higher bits, 1 = take lower bits) (Default = 0)",
"0");
- option_parser_register(opp, "-Seperate_Write_Queue_Enable", OPT_BOOL, &seperate_write_queue_enabled,
+ option_parser_register(opp, "-dram_seperate_write_queue_enable", OPT_BOOL, &seperate_write_queue_enabled,
"Seperate_Write_Queue_Enable",
"0");
- option_parser_register(opp, "-Write_Queue_Size", OPT_CSTR, &write_queue_size_opt,
+ option_parser_register(opp, "-dram_write_queue_size", OPT_CSTR, &write_queue_size_opt,
"Write_Queue_Size",
"32:28:16");
- option_parser_register(opp, "-Elimnate_rw_turnaround", OPT_BOOL, &elimnate_rw_turnaround,
+ option_parser_register(opp, "-dram_elimnate_rw_turnaround", OPT_BOOL, &elimnate_rw_turnaround,
"elimnate_rw_turnaround i.e set tWTR and tRTW = 0",
"0");
option_parser_register(opp, "-icnt_flit_size", OPT_UINT32, &icnt_flit_size,
@@ -240,13 +240,13 @@ void shader_core_config::reg_options(class OptionParser * opp)
"per-shader L1 data cache config "
" {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}",
"none" );
- option_parser_register(opp, "-l1_banks", OPT_UINT32, &m_L1D_config.l1_banks,
+ option_parser_register(opp, "-gpgpu_l1_banks", OPT_UINT32, &m_L1D_config.l1_banks,
"The number of L1 cache banks",
"1");
- option_parser_register(opp, "-l1_latency", OPT_UINT32, &m_L1D_config.l1_latency,
+ option_parser_register(opp, "-gpgpu_l1_latency", OPT_UINT32, &m_L1D_config.l1_latency,
"L1 Hit Latency",
"1");
- option_parser_register(opp, "-smem_latency", OPT_UINT32, &smem_latency,
+ option_parser_register(opp, "-gpgpu_smem_latency", OPT_UINT32, &smem_latency,
"smem Latency",
"3");
option_parser_register(opp, "-gpgpu_cache:dl1PrefL1", OPT_CSTR, &m_L1D_config.m_config_stringPrefL1,
@@ -257,7 +257,7 @@ void shader_core_config::reg_options(class OptionParser * opp)
"per-shader L1 data cache config "
" {<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq> | none}",
"none" );
- option_parser_register(opp, "-gmem_skip_L1D", OPT_BOOL, &gmem_skip_L1D,
+ option_parser_register(opp, "-gpgpu_gmem_skip_L1D", OPT_BOOL, &gmem_skip_L1D,
"global memory access skip L1D cache (implements -Xptxas -dlcm=cg, default=no skip)",
"0");
@@ -306,7 +306,7 @@ void shader_core_config::reg_options(class OptionParser * opp)
option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size,
"Size of shared memory per shader core (default 16kB)",
"16384");
- option_parser_register(opp, "-adaptive_cache_config", OPT_UINT32, &adaptive_cache_config,
+ option_parser_register(opp, "-gpgpu_adaptive_cache_config", OPT_UINT32, &adaptive_cache_config,
"adaptive_cache_config",
"0");
option_parser_register(opp, "-gpgpu_shmem_sizeDefault", OPT_UINT32, &gpgpu_shmem_sizeDefault,
@@ -327,7 +327,7 @@ void shader_core_config::reg_options(class OptionParser * opp)
option_parser_register(opp, "-gpgpu_shmem_warp_parts", OPT_INT32, &mem_warp_parts,
"Number of portions a warp is divided into for shared memory bank conflict check ",
"2");
- option_parser_register(opp, "-mem_unit_ports", OPT_INT32, &mem_unit_ports,
+ option_parser_register(opp, "-gpgpu_mem_unit_ports", OPT_INT32, &mem_unit_ports,
"The number of memory transactions allowed per core cycle",
"1");
option_parser_register(opp, "-gpgpu_shmem_warp_parts", OPT_INT32, &mem_warp_parts,
@@ -348,10 +348,10 @@ void shader_core_config::reg_options(class OptionParser * opp)
option_parser_register(opp, "-gpgpu_reg_bank_use_warp_id", OPT_BOOL, &gpgpu_reg_bank_use_warp_id,
"Use warp ID in mapping registers to banks (default = off)",
"0");
- option_parser_register(opp, "-sub_core_model", OPT_BOOL, &sub_core_model,
+ option_parser_register(opp, "-gpgpu_sub_core_model", OPT_BOOL, &sub_core_model,
"Sub Core Volta/Pascal model (default = off)",
"0");
- option_parser_register(opp, "-enable_specialized_operand_collector", OPT_BOOL, &enable_specialized_operand_collector,
+ option_parser_register(opp, "-gpgpu_enable_specialized_operand_collector", OPT_BOOL, &enable_specialized_operand_collector,
"enable_specialized_operand_collector",
"1");
option_parser_register(opp, "-gpgpu_operand_collector_num_units_sp", OPT_INT32, &gpgpu_operand_collector_num_units_sp,
@@ -467,15 +467,32 @@ void shader_core_config::reg_options(class OptionParser * opp)
option_parser_register(opp, "-gpgpu_concurrent_kernel_sm", OPT_BOOL, &gpgpu_concurrent_kernel_sm,
"Support concurrent kernels on a SM (default = disabled)",
"0");
- option_parser_register(opp, "-perfect_inst_const_cache", OPT_BOOL, &perfect_inst_const_cache,
+ option_parser_register(opp, "-gpgpu_perfect_inst_const_cache", OPT_BOOL, &perfect_inst_const_cache,
"perfect inst and const cache mode, so all inst and const hits in the cache(default = disabled)",
"0");
- option_parser_register(opp, "-inst_fetch_throughput", OPT_INT32, &inst_fetch_throughput,
+ option_parser_register(opp, "-gpgpu_inst_fetch_throughput", OPT_INT32, &inst_fetch_throughput,
"the number of fetched intruction per warp each cycle",
"1");
option_parser_register(opp, "-gpgpu_reg_file_port_throughput", OPT_INT32, &reg_file_port_throughput,
"the number ports of the register file",
"1");
+
+ //used for trace-driven mode
+ option_parser_register(opp, "-trace_opcode_latency_initiation_int", OPT_CSTR, &trace_opcode_latency_initiation_int,
+ "Opcode latencies and initiation for integers in trace driven mode <latency,initiation>",
+ "4,1");
+ option_parser_register(opp, "-trace_opcode_latency_initiation_sp", OPT_CSTR, &trace_opcode_latency_initiation_sp,
+ "Opcode latencies and initiation for sp in trace driven mode <latency,initiation>",
+ "4,1");
+ option_parser_register(opp, "-trace_opcode_latency_initiation_dp", OPT_CSTR, &trace_opcode_latency_initiation_dp,
+ "Opcode latencies and initiation for dp in trace driven mode <latency,initiation>",
+ "4,1");
+ option_parser_register(opp, "-trace_opcode_latency_initiation_sfu", OPT_CSTR, &trace_opcode_latency_initiation_sfu,
+ "Opcode latencies and initiation for sfu in trace driven mode <latency,initiation>",
+ "4,1");
+ option_parser_register(opp, "-trace_opcode_latency_initiation_tensor", OPT_CSTR, &trace_opcode_latency_initiation_tensor,
+ "Opcode latencies and initiation for tensor in trace driven mode <latency,initiation>",
+ "4,1");
}
void gpgpu_sim_config::reg_options(option_parser_t opp)
diff --git a/src/gpgpu-sim/icnt_wrapper.cc b/src/gpgpu-sim/icnt_wrapper.cc
index e449bf1..6e3e596 100644
--- a/src/gpgpu-sim/icnt_wrapper.cc
+++ b/src/gpgpu-sim/icnt_wrapper.cc
@@ -179,12 +179,12 @@ void icnt_reg_options( class OptionParser * opp )
//parameters for local xbar
- option_parser_register(opp, "-inct_in_buffer_limit", OPT_UINT32, &g_inct_config.in_buffer_limit, "in_buffer_limit", "64");
- option_parser_register(opp, "-inct_out_buffer_limit", OPT_UINT32, &g_inct_config.out_buffer_limit, "out_buffer_limit", "64");
- option_parser_register(opp, "-inct_subnets", OPT_UINT32, &g_inct_config.subnets, "subnets", "2");
- option_parser_register(opp, "-arbiter_algo", OPT_UINT32, &g_inct_config.arbiter_algo, "arbiter_algo", "1");
- option_parser_register(opp, "-inct_verbose", OPT_UINT32, &g_inct_config.verbose, "inct_verbose", "0");
- option_parser_register(opp, "-inct_grant_cycles", OPT_UINT32, &g_inct_config.grant_cycles, "grant_cycles", "1");
+ option_parser_register(opp, "-icnt_in_buffer_limit", OPT_UINT32, &g_inct_config.in_buffer_limit, "in_buffer_limit", "64");
+ option_parser_register(opp, "-icnt_out_buffer_limit", OPT_UINT32, &g_inct_config.out_buffer_limit, "out_buffer_limit", "64");
+ option_parser_register(opp, "-icnt_subnets", OPT_UINT32, &g_inct_config.subnets, "subnets", "2");
+ option_parser_register(opp, "-icnt_arbiter_algo", OPT_UINT32, &g_inct_config.arbiter_algo, "arbiter_algo", "1");
+ option_parser_register(opp, "-icnt_verbose", OPT_UINT32, &g_inct_config.verbose, "inct_verbose", "0");
+ option_parser_register(opp, "-icnt_grant_cycles", OPT_UINT32, &g_inct_config.grant_cycles, "grant_cycles", "1");
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 65ec113..900ec90 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -3088,7 +3088,7 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const
switch (adaptive_cache_config) {
case FIXED:
break;
- case VOLTA: {
+ case ADAPTIVE_VOLTA: {
//For Volta, we assign the remaining shared memory to L1 cache
//For more info about adaptive cache, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
//assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 665e3a5..ca85903 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1527,6 +1527,13 @@ class shader_core_config : public core_config
unsigned inst_fetch_throughput;
unsigned reg_file_port_throughput;
+ char* trace_opcode_latency_initiation_int;
+ char* trace_opcode_latency_initiation_sp;
+ char* trace_opcode_latency_initiation_dp;
+ char* trace_opcode_latency_initiation_sfu;
+ char* trace_opcode_latency_initiation_tensor;
+
+
};
struct shader_core_stats_pod {
diff --git a/src/trace-driven/gpgpusim_trace_driven_main.cc b/src/trace-driven/gpgpusim_trace_driven_main.cc
index bedac4c..5e07ace 100644
--- a/src/trace-driven/gpgpusim_trace_driven_main.cc
+++ b/src/trace-driven/gpgpusim_trace_driven_main.cc
@@ -48,6 +48,7 @@ int main ( int argc, const char **argv )
//prints stats
trace_parser tracer(m_gpgpu_sim->get_config().get_traces_filename(), m_gpgpu_sim, m_gpgpu_context);
+ trace_config config(m_gpgpu_sim);
std::vector<std::string> commandlist = tracer.parse_kernellist_file();
bool first_kernel=true;
@@ -69,7 +70,7 @@ int main ( int argc, const char **argv )
first_kernel = false;
continue;
}
- kernel_info = tracer.parse_kernel_info(commandlist[i]);
+ kernel_info = tracer.parse_kernel_info(commandlist[i], &config);
m_gpgpu_sim->launch(kernel_info);
}
diff --git a/src/trace-driven/kepler_opcode.h b/src/trace-driven/kepler_opcode.h
index f2bbc90..4aa8e0f 100644
--- a/src/trace-driven/kepler_opcode.h
+++ b/src/trace-driven/kepler_opcode.h
@@ -99,12 +99,13 @@ static const std::unordered_map<std::string,OpcodeChar> Kepler_OpcodeMap = {
//Load/Store Instructions
//For now, we ignore constant loads, consider it as ALU_OP, TO DO
{"LDC", OpcodeChar(OP_LDC, ALU_OP)},
- {"LD", OpcodeChar(OP_LD, LOAD_OP)},
+ //in Kepler, LD is load global so set it to LDG
+ {"LD", OpcodeChar(OP_LDG, LOAD_OP)},
{"LDG", OpcodeChar(OP_LDG, LOAD_OP)},
{"LDL", OpcodeChar(OP_LDL, LOAD_OP)},
{"LDS", OpcodeChar(OP_LDS, LOAD_OP)},
{"LDSLK", OpcodeChar(OP_LDSLK, LOAD_OP)},
- {"ST", OpcodeChar(OP_ST, STORE_OP)},
+ {"ST", OpcodeChar(OP_STG, STORE_OP)},
{"STL", OpcodeChar(OP_STL, STORE_OP)},
{"STS", OpcodeChar(OP_STS, STORE_OP)},
{"STSCUL", OpcodeChar(OP_STSCUL, STORE_OP)},
diff --git a/src/trace-driven/trace_driven.cc b/src/trace-driven/trace_driven.cc
index 35e953e..22c527e 100644
--- a/src/trace-driven/trace_driven.cc
+++ b/src/trace-driven/trace_driven.cc
@@ -98,7 +98,7 @@ void trace_parser::parse_memcpy_info(const std::string& memcpy_command, size_t&
ss>>std::dec>>count;
}
-trace_kernel_info_t* trace_parser::parse_kernel_info(const std::string& kerneltraces_filepath) {
+trace_kernel_info_t* trace_parser::parse_kernel_info(const std::string& kerneltraces_filepath, trace_config* config) {
ifs.open(kerneltraces_filepath.c_str());
@@ -167,7 +167,7 @@ trace_kernel_info_t* trace_parser::parse_kernel_info(const std::string& kerneltr
dim3 blockDim(tb_dim_x, tb_dim_y, tb_dim_z);
trace_function_info* function_info = new trace_function_info(info, m_gpgpu_context);
function_info->set_name(kernel_name.c_str());
- trace_kernel_info_t* kernel_info = new trace_kernel_info_t(gridDim, blockDim, binary_verion, function_info, &ifs, m_gpgpu_sim, m_gpgpu_context);
+ trace_kernel_info_t* kernel_info = new trace_kernel_info_t(gridDim, blockDim, binary_verion, function_info, &ifs, m_gpgpu_sim, m_gpgpu_context, config);
return kernel_info;
}
@@ -211,11 +211,12 @@ address_type trace_shd_warp_t::get_pc(){
return warp_traces[trace_pc].pc;
}
-trace_kernel_info_t::trace_kernel_info_t(dim3 gridDim, dim3 blockDim, unsigned m_binary_verion, trace_function_info* m_function_info, std::ifstream* inputstream, gpgpu_sim * gpgpu_sim, gpgpu_context* gpgpu_context):kernel_info_t(gridDim, blockDim, m_function_info) {
+trace_kernel_info_t::trace_kernel_info_t(dim3 gridDim, dim3 blockDim, unsigned m_binary_verion, trace_function_info* m_function_info, std::ifstream* inputstream, gpgpu_sim * gpgpu_sim, gpgpu_context* gpgpu_context, class trace_config* config):kernel_info_t(gridDim, blockDim, m_function_info) {
ifs = inputstream;
m_gpgpu_sim = gpgpu_sim;
m_gpgpu_context = gpgpu_context;
binary_verion = m_binary_verion;
+ m_tconfig = config;
//resolve the binary version
if(m_binary_verion == VOLTA_BINART_VERSION)
@@ -285,8 +286,8 @@ bool trace_kernel_info_t::get_next_threadblock_traces(std::vector<std::vector<tr
}
else {
assert(start_of_tb_stream_found);
- trace_warp_inst_t inst(m_gpgpu_sim->getShaderCoreConfig(), m_gpgpu_context);
- inst.parse_from_string(line, OpcodeMap, binary_verion);
+ trace_warp_inst_t inst(m_gpgpu_sim->getShaderCoreConfig(), m_gpgpu_context, m_tconfig);
+ inst.parse_from_string(line, OpcodeMap);
threadblock_traces[warp_id]->push_back(inst);
}
}
@@ -323,7 +324,7 @@ unsigned trace_warp_inst_t::get_datawidth_from_opcode(const std::vector<std::str
return 4; //default is 4 bytes
}
-bool trace_warp_inst_t::parse_from_string(std::string trace, const std::unordered_map<std::string,OpcodeChar>* OpcodeMap, unsigned binary_verion){
+bool trace_warp_inst_t::parse_from_string(std::string trace, const std::unordered_map<std::string,OpcodeChar>* OpcodeMap){
std::stringstream ss;
ss.str(trace);
@@ -473,7 +474,7 @@ bool trace_warp_inst_t::parse_from_string(std::string trace, const std::unordere
//remove redundant registers
//fill latency and initl
- set_latency(op);
+ m_tconfig->set_latency(op, latency, initiation_interval);
//fill addresses
if(mem_width > 0) {
@@ -548,10 +549,7 @@ bool trace_warp_inst_t::parse_from_string(std::string trace, const std::unordere
//right now, we consider all loads are shared.
assert(mem_width>0);
data_size = get_datawidth_from_opcode(opcode_tokens);
- if(binary_verion == KEPLER_BINART_VERSION)
- space.set_type(global_space);
- else
- space.set_type(shared_space);
+ space.set_type(shared_space);
if(m_opcode == OP_LD)
memory_op = memory_load;
else
@@ -584,59 +582,29 @@ bool trace_warp_inst_t::parse_from_string(std::string trace, const std::unordere
return true;
}
-void trace_warp_inst_t::set_latency(unsigned category)
+trace_config::trace_config(gpgpu_sim* m_gpgpu_sim){
+
+ this->m_gpgpu_sim=m_gpgpu_sim;
+ parse_config();
+}
+
+void trace_config::parse_config()
{
- unsigned int_latency[5];
- unsigned fp_latency[5];
- unsigned dp_latency[5];
- unsigned sfu_latency;
- unsigned tensor_latency;
- unsigned int_init[5];
- unsigned fp_init[5];
- unsigned dp_init[5];
- unsigned sfu_init;
- unsigned tensor_init;
- /*
- * [0] ADD,SUB
- * [1] MAX,Min
- * [2] MUL
- * [3] MAD
- * [4] DIV
- */
- sscanf(m_gpgpu_context->func_sim->opcode_latency_int, "%u,%u,%u,%u,%u",
- &int_latency[0],&int_latency[1],&int_latency[2],
- &int_latency[3],&int_latency[4]);
- sscanf(m_gpgpu_context->func_sim->opcode_latency_fp, "%u,%u,%u,%u,%u",
- &fp_latency[0],&fp_latency[1],&fp_latency[2],
- &fp_latency[3],&fp_latency[4]);
- sscanf(m_gpgpu_context->func_sim->opcode_latency_dp, "%u,%u,%u,%u,%u",
- &dp_latency[0],&dp_latency[1],&dp_latency[2],
- &dp_latency[3],&dp_latency[4]);
- sscanf(m_gpgpu_context->func_sim->opcode_latency_sfu, "%u",
- &sfu_latency);
- sscanf(m_gpgpu_context->func_sim->opcode_latency_tensor, "%u",
- &tensor_latency);
- sscanf(m_gpgpu_context->func_sim->opcode_initiation_int, "%u,%u,%u,%u,%u",
- &int_init[0],&int_init[1],&int_init[2],
- &int_init[3],&int_init[4]);
- sscanf(m_gpgpu_context->func_sim->opcode_initiation_fp, "%u,%u,%u,%u,%u",
- &fp_init[0],&fp_init[1],&fp_init[2],
- &fp_init[3],&fp_init[4]);
- sscanf(m_gpgpu_context->func_sim->opcode_initiation_dp, "%u,%u,%u,%u,%u",
- &dp_init[0],&dp_init[1],&dp_init[2],
- &dp_init[3],&dp_init[4]);
- sscanf(m_gpgpu_context->func_sim->opcode_initiation_sfu, "%u",
- &sfu_init);
- sscanf(m_gpgpu_context->func_sim->opcode_initiation_tensor, "%u",
- &tensor_init);
- sscanf(m_gpgpu_context->func_sim->cdp_latency_str, "%u,%u,%u,%u,%u",
- &m_gpgpu_context->func_sim->cdp_latency[0],
- &m_gpgpu_context->func_sim->cdp_latency[1],
- &m_gpgpu_context->func_sim->cdp_latency[2],
- &m_gpgpu_context->func_sim->cdp_latency[3],
- &m_gpgpu_context->func_sim->cdp_latency[4]);
+ sscanf(m_gpgpu_sim->getShaderCoreConfig()->trace_opcode_latency_initiation_int, "%u,%u",
+ &int_latency,&int_init);
+ sscanf(m_gpgpu_sim->getShaderCoreConfig()->trace_opcode_latency_initiation_sp, "%u,%u",
+ &fp_latency,&fp_init);
+ sscanf(m_gpgpu_sim->getShaderCoreConfig()->trace_opcode_latency_initiation_dp, "%u,%u",
+ &dp_latency,&dp_init);
+ sscanf(m_gpgpu_sim->getShaderCoreConfig()->trace_opcode_latency_initiation_sfu, "%u,%u",
+ &sfu_latency,&sfu_init);
+ sscanf(m_gpgpu_sim->getShaderCoreConfig()->trace_opcode_latency_initiation_tensor, "%u,%u",
+ &tensor_latency,&tensor_init);
+}
+void trace_config::set_latency(unsigned category, unsigned& latency, unsigned& initiation_interval)
+{
initiation_interval = latency = 1;
switch(category){
@@ -645,16 +613,16 @@ void trace_warp_inst_t::set_latency(unsigned category)
case BRANCH_OP:
case CALL_OPS:
case RET_OPS:
- latency = int_latency[0];
- initiation_interval = int_init[0];
+ latency = int_latency;
+ initiation_interval = int_init;
break;
case SP_OP:
- latency = fp_latency[0];
- initiation_interval = fp_init[0];
+ latency = fp_latency;
+ initiation_interval = fp_init;
break;
case DP_OP:
- latency = dp_latency[0];
- initiation_interval = dp_init[0];
+ latency = dp_latency;
+ initiation_interval = dp_init;
break;
case SFU_OP:
latency = sfu_latency;
diff --git a/src/trace-driven/trace_driven.h b/src/trace-driven/trace_driven.h
index 9539e6d..2888f86 100644
--- a/src/trace-driven/trace_driven.h
+++ b/src/trace-driven/trace_driven.h
@@ -37,18 +37,20 @@ public:
trace_warp_inst_t() {
m_gpgpu_context=NULL;
m_opcode=0;
+ m_tconfig=NULL;
}
- trace_warp_inst_t(const class core_config *config, gpgpu_context* gpgpu_context ):warp_inst_t(config) {
+ trace_warp_inst_t(const class core_config *config, gpgpu_context* gpgpu_context, class trace_config* tconfig ):warp_inst_t(config) {
m_gpgpu_context = gpgpu_context;
m_opcode=0;
+ m_tconfig=tconfig;
}
- bool parse_from_string(std::string trace, const std::unordered_map<std::string,OpcodeChar>* OpcodeMap, unsigned binary_verion);
+ bool parse_from_string(std::string trace, const std::unordered_map<std::string,OpcodeChar>* OpcodeMap);
private:
- void set_latency(unsigned cat);
gpgpu_context* m_gpgpu_context;
+ class trace_config* m_tconfig;
unsigned m_opcode;
bool check_opcode_contain(const std::vector<std::string>& opcode, std::string param);
unsigned get_datawidth_from_opcode(const std::vector<std::string>& opcode);
@@ -56,7 +58,7 @@ private:
class trace_kernel_info_t: public kernel_info_t {
public:
- trace_kernel_info_t(dim3 gridDim, dim3 blockDim, unsigned m_binary_verion, trace_function_info* m_function_info, std::ifstream* inputstream, gpgpu_sim * gpgpu_sim, gpgpu_context* gpgpu_context);
+ trace_kernel_info_t(dim3 gridDim, dim3 blockDim, unsigned m_binary_verion, trace_function_info* m_function_info, std::ifstream* inputstream, gpgpu_sim * gpgpu_sim, gpgpu_context* gpgpu_context, class trace_config* config);
bool get_next_threadblock_traces(std::vector<std::vector<trace_warp_inst_t>*> threadblock_traces);
@@ -64,19 +66,35 @@ private:
std::ifstream* ifs;
gpgpu_sim * m_gpgpu_sim;
gpgpu_context* m_gpgpu_context;
+ trace_config* m_tconfig;
unsigned binary_verion;
const std::unordered_map<std::string,OpcodeChar>* OpcodeMap;
};
+class trace_config {
+public:
+ trace_config(gpgpu_sim * m_gpgpu_sim);
+
+ void set_latency(unsigned category, unsigned& latency, unsigned& initiation_interval);
+ void parse_config();
+
+
+private:
+
+ unsigned int_latency, fp_latency, dp_latency, sfu_latency, tensor_latency;
+ unsigned int_init, fp_init, dp_init, sfu_init, tensor_init;
+ gpgpu_sim* m_gpgpu_sim;
+
+};
class trace_parser {
public:
trace_parser(const char* kernellist_filepath, gpgpu_sim * m_gpgpu_sim, gpgpu_context* m_gpgpu_context);
std::vector<std::string> parse_kernellist_file();
- trace_kernel_info_t* parse_kernel_info(const std::string& kerneltraces_filepath);
+ trace_kernel_info_t* parse_kernel_info(const std::string& kerneltraces_filepath, trace_config* config);
void parse_memcpy_info(const std::string& memcpy_command, size_t& add, size_t& count);
void kernel_finalizer(trace_kernel_info_t* kernel_info);
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 02:41:08 +0000