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-rw-r--r--src/abstract_hardware_model.cc6
-rw-r--r--src/abstract_hardware_model.h19
-rw-r--r--src/cuda-sim/cuda-sim.cc151
-rw-r--r--src/cuda-sim/cuda-sim.h98
-rw-r--r--src/cuda-sim/cuda_device_runtime.cc7
-rw-r--r--src/cuda-sim/cuda_device_runtime.h18
-rw-r--r--src/cuda-sim/ptx_ir.cc16
-rw-r--r--src/cuda-sim/ptx_ir.h19
-rw-r--r--src/cuda-sim/ptx_loader.cc12
-rw-r--r--src/cuda-sim/ptx_loader.h7
-rw-r--r--src/cuda-sim/ptx_parser.cc12
-rw-r--r--src/cuda-sim/ptx_parser.h1
-rw-r--r--src/cuda-sim/ptxinfo.l4
-rw-r--r--src/debug.h2
-rw-r--r--src/gpgpu-sim/gpu-sim.cc20
-rw-r--r--src/gpgpu-sim/gpu-sim.h17
-rw-r--r--src/gpgpu-sim/mem_latency_stat.cc2
-rw-r--r--src/gpgpu-sim/mem_latency_stat.h4
-rw-r--r--src/gpgpu-sim/power_interface.cc2
-rw-r--r--src/gpgpu-sim/power_interface.h2
-rw-r--r--src/gpgpu-sim/power_stat.cc6
-rw-r--r--src/gpgpu-sim/power_stat.h6
-rw-r--r--src/gpgpu-sim/shader.cc26
-rw-r--r--src/gpgpu-sim/shader.h18
-rw-r--r--src/gpgpusim_entrypoint.cc14
-rw-r--r--src/gpgpusim_entrypoint.h1
-rw-r--r--src/stream_manager.cc5
27 files changed, 278 insertions, 217 deletions
diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index 7755477..ef09051 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -39,6 +39,7 @@
#include <sys/stat.h>
#include <sstream>
#include <iostream>
+#include "../libcuda/gpgpu_context.h"
unsigned mem_access_t::sm_next_access_uid = 0;
unsigned warp_inst_t::sm_next_uid = 0;
@@ -173,9 +174,10 @@ void gpgpu_functional_sim_config::ptx_set_tex_cache_linesize(unsigned linesize)
m_texcache_linesize = linesize;
}
-gpgpu_t::gpgpu_t( const gpgpu_functional_sim_config &config )
+gpgpu_t::gpgpu_t( const gpgpu_functional_sim_config &config, gpgpu_context* ctx )
: m_function_model_config(config)
{
+ gpgpu_ctx = ctx;
m_global_mem = new memory_space_impl<8192>("global",64*1024);
m_tex_mem = new memory_space_impl<8192>("tex",64*1024);
@@ -944,7 +946,7 @@ void simt_stack::print (FILE *fout) const
} else {
fprintf(fout," " );
}
- ptx_print_insn( stack_entry.m_pc, fout );
+ m_gpu->gpgpu_ctx->func_sim->ptx_print_insn( stack_entry.m_pc, fout );
fprintf(fout,"\n");
}
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 68cb693..8ef8376 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -31,6 +31,8 @@
// Forward declarations
class gpgpu_sim;
class kernel_info_t;
+class gpgpu_context;
+
//Set a hard limit of 32 CTAs per shader [cuda only has 8]
#define MAX_CTA_PER_SHADER 32
@@ -345,9 +347,11 @@ public:
mutable bool volta_cache_config_set;
};
-struct core_config {
- core_config()
- {
+class core_config {
+ public:
+ core_config(gpgpu_context* ctx)
+ {
+ gpgpu_ctx = ctx;
m_valid = false;
num_shmem_bank=16;
shmem_limited_broadcast = false;
@@ -359,6 +363,8 @@ struct core_config {
bool m_valid;
unsigned warp_size;
+ // backward pointer
+ class gpgpu_context* gpgpu_ctx;
// off-chip memory request architecture parameters
int gpgpu_coalesce_arch;
@@ -529,7 +535,9 @@ private:
class gpgpu_t {
public:
- gpgpu_t( const gpgpu_functional_sim_config &config );
+ gpgpu_t( const gpgpu_functional_sim_config &config, gpgpu_context* ctx );
+ // backward pointer
+ class gpgpu_context* gpgpu_ctx;
int checkpoint_option;
int checkpoint_kernel;
int checkpoint_CTA;
@@ -930,7 +938,7 @@ public:
m_empty=true;
m_config=NULL;
}
- warp_inst_t( const core_config *config )
+ warp_inst_t( const core_config *config )
{
m_uid=0;
assert(config->warp_size<=MAX_WARP_SIZE);
@@ -1101,7 +1109,6 @@ public:
unsigned get_uid() const { return m_uid; }
unsigned get_schd_id() const { return m_scheduler_id; }
-
protected:
unsigned m_uid;
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 261d605..7ff869c 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -51,27 +51,14 @@ typedef void * yyscan_t;
#include "decuda_pred_table/decuda_pred_table.h"
#include "../stream_manager.h"
#include "cuda_device_runtime.h"
+#include "../../libcuda/gpgpu_context.h"
-int gpgpu_ptx_instruction_classification;
-void ** g_inst_classification_stat = NULL;
-void ** g_inst_op_classification_stat= NULL;
-int g_ptx_kernel_count = -1; // used for classification stat collection purposes
int g_debug_execution = 0;
-int g_debug_thread_uid = 0;
addr_t g_debug_pc = 0xBEEF1518;
// Output debug information to file options
-int cp_count;
-int cp_cta_resume;
-unsigned g_ptx_sim_num_insn = 0;
-unsigned gpgpu_param_num_shaders = 0;
-char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp,*opcode_latency_sfu,*opcode_latency_tensor;
-char *opcode_initiation_int, *opcode_initiation_fp, *opcode_initiation_dp,*opcode_initiation_sfu,*opcode_initiation_tensor;
-char *cdp_latency_str;
-unsigned cdp_latency[5];
-
-void ptx_opcocde_latency_options (option_parser_t opp) {
+void cuda_sim::ptx_opcocde_latency_options (option_parser_t opp) {
option_parser_register(opp, "-ptx_opcode_latency_int", OPT_CSTR, &opcode_latency_int,
"Opcode latencies for integers <ADD,MAX,MUL,MAD,DIV>"
"Default 1,1,19,25,145",
@@ -120,8 +107,6 @@ cudaLaunchDeviceV2_init_perWarp, cudaLaunchDevicV2_perKernel>"
"7200,8000,100,12000,1600");
}
-static address_type get_converge_point(address_type pc);
-
void gpgpu_t::gpgpu_ptx_sim_bindNameToTexture(const char* name, const struct textureReference* texref, int dim, int readmode, int ext)
{
std::string texname(name);
@@ -231,8 +216,6 @@ void gpgpu_t::gpgpu_ptx_sim_unbindTexture(const struct textureReference* texref)
m_NameToTextureInfo.erase(texname);
}
-unsigned g_assemble_code_next_pc=0;
-std::map<unsigned,function_info*> g_pc_to_finfo;
std::vector<ptx_instruction*> function_info::s_g_pc_to_insn;
#define MAX_INST_SIZE 8 /*bytes*/
@@ -252,7 +235,7 @@ void function_info::ptx_assemble()
fflush(stdout);
std::list<ptx_instruction*>::iterator i;
- addr_t PC = g_assemble_code_next_pc; // globally unique address (across functions)
+ addr_t PC = gpgpu_ctx->func_sim->g_assemble_code_next_pc; // globally unique address (across functions)
// start function on an aligned address
for( unsigned i=0; i < (PC%MAX_INST_SIZE); i++ )
s_g_pc_to_insn.push_back((ptx_instruction*)NULL);
@@ -269,7 +252,7 @@ void function_info::ptx_assemble()
const symbol *l = pI->get_label();
labels[l->name()] = n;
} else {
- g_pc_to_finfo[PC] = this;
+ gpgpu_ctx->func_sim->g_pc_to_finfo[PC] = this;
m_instr_mem[n] = pI;
s_g_pc_to_insn.push_back(pI);
assert(pI == s_g_pc_to_insn[PC]);
@@ -284,7 +267,7 @@ void function_info::ptx_assemble()
PC += pI->inst_size();
}
}
- g_assemble_code_next_pc=PC;
+ gpgpu_ctx->func_sim->g_assemble_code_next_pc=PC;
for ( unsigned ii=0; ii < n; ii += m_instr_mem[ii]->inst_size() ) { // handle branch instructions
ptx_instruction *pI = m_instr_mem[ii];
if ( pI->get_opcode() == BRA_OP || pI->get_opcode() == BREAKADDR_OP || pI->get_opcode() == CALLP_OP) {
@@ -509,7 +492,7 @@ void gpgpu_t::gpu_memset( size_t dst_start_addr, int c, size_t count )
}
}
-void ptx_print_insn( address_type pc, FILE *fp )
+void cuda_sim::ptx_print_insn( address_type pc, FILE *fp )
{
std::map<unsigned,function_info*>::iterator f = g_pc_to_finfo.find(pc);
if( f == g_pc_to_finfo.end() ) {
@@ -521,7 +504,7 @@ void ptx_print_insn( address_type pc, FILE *fp )
finfo->print_insn(pc,fp);
}
-std::string ptx_get_insn_str( address_type pc )
+std::string cuda_sim::ptx_get_insn_str( address_type pc )
{
std::map<unsigned,function_info*>::iterator f = g_pc_to_finfo.find(pc);
if( f == g_pc_to_finfo.end() ) {
@@ -667,35 +650,38 @@ void ptx_instruction::set_opcode_and_latency()
* [3] MAD
* [4] DIV
*/
- sscanf(opcode_latency_int, "%u,%u,%u,%u,%u",
+ sscanf(gpgpu_ctx->func_sim->opcode_latency_int, "%u,%u,%u,%u,%u",
&int_latency[0],&int_latency[1],&int_latency[2],
&int_latency[3],&int_latency[4]);
- sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u",
+ sscanf(gpgpu_ctx->func_sim->opcode_latency_fp, "%u,%u,%u,%u,%u",
&fp_latency[0],&fp_latency[1],&fp_latency[2],
&fp_latency[3],&fp_latency[4]);
- sscanf(opcode_latency_dp, "%u,%u,%u,%u,%u",
+ sscanf(gpgpu_ctx->func_sim->opcode_latency_dp, "%u,%u,%u,%u,%u",
&dp_latency[0],&dp_latency[1],&dp_latency[2],
&dp_latency[3],&dp_latency[4]);
- sscanf(opcode_latency_sfu, "%u",
+ sscanf(gpgpu_ctx->func_sim->opcode_latency_sfu, "%u",
&sfu_latency);
- sscanf(opcode_latency_tensor, "%u",
+ sscanf(gpgpu_ctx->func_sim->opcode_latency_tensor, "%u",
&tensor_latency);
- sscanf(opcode_initiation_int, "%u,%u,%u,%u,%u",
+ sscanf(gpgpu_ctx->func_sim->opcode_initiation_int, "%u,%u,%u,%u,%u",
&int_init[0],&int_init[1],&int_init[2],
&int_init[3],&int_init[4]);
- sscanf(opcode_initiation_fp, "%u,%u,%u,%u,%u",
+ sscanf(gpgpu_ctx->func_sim->opcode_initiation_fp, "%u,%u,%u,%u,%u",
&fp_init[0],&fp_init[1],&fp_init[2],
&fp_init[3],&fp_init[4]);
- sscanf(opcode_initiation_dp, "%u,%u,%u,%u,%u",
+ sscanf(gpgpu_ctx->func_sim->opcode_initiation_dp, "%u,%u,%u,%u,%u",
&dp_init[0],&dp_init[1],&dp_init[2],
&dp_init[3],&dp_init[4]);
- sscanf(opcode_initiation_sfu, "%u",
+ sscanf(gpgpu_ctx->func_sim->opcode_initiation_sfu, "%u",
&sfu_init);
- sscanf(opcode_initiation_tensor, "%u",
+ sscanf(gpgpu_ctx->func_sim->opcode_initiation_tensor, "%u",
&tensor_init);
- sscanf(cdp_latency_str, "%u,%u,%u,%u,%u",
- &cdp_latency[0],&cdp_latency[1],&cdp_latency[2],
- &cdp_latency[3],&cdp_latency[4]);
+ sscanf(gpgpu_ctx->func_sim->cdp_latency_str, "%u,%u,%u,%u,%u",
+ &gpgpu_ctx->func_sim->cdp_latency[0],
+ &gpgpu_ctx->func_sim->cdp_latency[1],
+ &gpgpu_ctx->func_sim->cdp_latency[2],
+ &gpgpu_ctx->func_sim->cdp_latency[3],
+ &gpgpu_ctx->func_sim->cdp_latency[4]);
if(!m_operands.empty()){
std::vector<operand_info>::iterator it;
@@ -1104,7 +1090,7 @@ void ptx_instruction::pre_decode()
}
// get reconvergence pc
- reconvergence_pc = get_converge_point(pc);
+ reconvergence_pc = gpgpu_ctx->func_sim->get_converge_point(pc);
m_decoded=true;
}
@@ -1468,7 +1454,7 @@ void function_info::ptx_jit_config(std::map<unsigned long long, size_t> mallocPt
}
template<int activate_level>
-bool ptx_debug_exec_dump_cond(int thd_uid, addr_t pc)
+bool cuda_sim::ptx_debug_exec_dump_cond(int thd_uid, addr_t pc)
{
if (g_debug_execution >= activate_level) {
// check each type of debug dump constraint to filter out dumps
@@ -1485,7 +1471,7 @@ bool ptx_debug_exec_dump_cond(int thd_uid, addr_t pc)
return false;
}
-void init_inst_classification_stat()
+void cuda_sim::init_inst_classification_stat()
{
static std::set<unsigned> init;
if( init.find(g_ptx_kernel_count) != init.end() )
@@ -1554,7 +1540,8 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
}
if ( g_debug_execution >= 6 || m_gpu->get_config().get_ptx_inst_debug_to_file()) {
- if ( (g_debug_thread_uid==0) || (get_uid() == (unsigned)g_debug_thread_uid) ) {
+ if ( (m_gpu->gpgpu_ctx->func_sim->g_debug_thread_uid==0)
+ || (get_uid() == (unsigned)(m_gpu->gpgpu_ctx->func_sim->g_debug_thread_uid)) ) {
clear_modifiedregs();
enable_debug_trace();
@@ -1626,11 +1613,11 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
fflush(m_gpu->get_ptx_inst_debug_file());
}
- if ( ptx_debug_exec_dump_cond<5>(get_uid(), pc) ) {
+ if ( m_gpu->gpgpu_ctx->func_sim->ptx_debug_exec_dump_cond<5>(get_uid(), pc) ) {
dim3 ctaid = get_ctaid();
dim3 tid = get_tid();
printf("%u [thd=%u][i=%u] : ctaid=(%u,%u,%u) tid=(%u,%u,%u) icount=%u [pc=%u] (%s:%u - %s) [0x%llx]\n",
- g_ptx_sim_num_insn,
+ m_gpu->gpgpu_ctx->func_sim->g_ptx_sim_num_insn,
get_uid(),
pI->uid(), ctaid.x,ctaid.y,ctaid.z,tid.x,tid.y,tid.z,
get_icount(),
@@ -1680,22 +1667,22 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
}
if ( g_debug_execution >= 6 ) {
- if ( ptx_debug_exec_dump_cond<6>(get_uid(), pc) )
+ if ( m_gpu->gpgpu_ctx->func_sim->ptx_debug_exec_dump_cond<6>(get_uid(), pc) )
dump_modifiedregs(stdout);
}
if ( g_debug_execution >= 10 ) {
- if ( ptx_debug_exec_dump_cond<10>(get_uid(), pc) )
+ if ( m_gpu->gpgpu_ctx->func_sim->ptx_debug_exec_dump_cond<10>(get_uid(), pc) )
dump_regs(stdout);
}
update_pc();
- g_ptx_sim_num_insn++;
+ m_gpu->gpgpu_ctx->func_sim->g_ptx_sim_num_insn++;
//not using it with functional simulation mode
if(!(this->m_functionalSimulationMode))
ptx_file_line_stats_add_exec_count(pI);
- if ( gpgpu_ptx_instruction_classification ) {
- init_inst_classification_stat();
+ if ( m_gpu->gpgpu_ctx->func_sim->gpgpu_ptx_instruction_classification ) {
+ m_gpu->gpgpu_ctx->func_sim->init_inst_classification_stat();
unsigned space_type=0;
switch ( pI->get_space().get_type() ) {
case global_space: space_type = 10; break;
@@ -1711,15 +1698,15 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
space_type = 0 ;
break;
}
- StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], op_classification);
- if (space_type) StatAddSample( g_inst_classification_stat[g_ptx_kernel_count], ( int )space_type);
- StatAddSample( g_inst_op_classification_stat[g_ptx_kernel_count], (int) pI->get_opcode() );
+ StatAddSample( m_gpu->gpgpu_ctx->func_sim->g_inst_classification_stat[m_gpu->gpgpu_ctx->func_sim->g_ptx_kernel_count], op_classification);
+ if (space_type) StatAddSample( m_gpu->gpgpu_ctx->func_sim->g_inst_classification_stat[m_gpu->gpgpu_ctx->func_sim->g_ptx_kernel_count], ( int )space_type);
+ StatAddSample( m_gpu->gpgpu_ctx->func_sim->g_inst_op_classification_stat[m_gpu->gpgpu_ctx->func_sim->g_ptx_kernel_count], (int) pI->get_opcode() );
}
- if ( (g_ptx_sim_num_insn % 100000) == 0 ) {
+ if ( (m_gpu->gpgpu_ctx->func_sim->g_ptx_sim_num_insn % 100000) == 0 ) {
dim3 ctaid = get_ctaid();
dim3 tid = get_tid();
DPRINTF(LIVENESS, "GPGPU-Sim PTX: %u instructions simulated : ctaid=(%u,%u,%u) tid=(%u,%u,%u)\n",
- g_ptx_sim_num_insn, ctaid.x,ctaid.y,ctaid.z,tid.x,tid.y,tid.z );
+ m_gpu->gpgpu_ctx->func_sim->g_ptx_sim_num_insn, ctaid.x,ctaid.y,ctaid.z,tid.x,tid.y,tid.z );
fflush(stdout);
}
@@ -1742,7 +1729,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id)
}
-void set_param_gpgpu_num_shaders(int num_shaders)
+void cuda_sim::set_param_gpgpu_num_shaders(int num_shaders)
{
gpgpu_param_num_shaders = num_shaders;
}
@@ -1824,7 +1811,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel,
assert( max_cta_per_sm > 0 );
//unsigned sm_idx = (tid/cta_size)*gpgpu_param_num_shaders + sid;
- unsigned sm_idx = hw_cta_id*gpgpu_param_num_shaders + sid;
+ unsigned sm_idx = hw_cta_id*gpu->gpgpu_ctx->func_sim->gpgpu_param_num_shaders + sid;
if ( shared_memory_lookup.find(sm_idx) == shared_memory_lookup.end() ) {
if ( g_debug_execution >= 1 ) {
@@ -1922,7 +1909,7 @@ size_t get_kernel_code_size( class function_info *entry )
}
-kernel_info_t *gpgpu_opencl_ptx_sim_init_grid(class function_info *entry,
+kernel_info_t *cuda_sim::gpgpu_opencl_ptx_sim_init_grid(class function_info *entry,
gpgpu_ptx_sim_arg_list_t args,
struct dim3 gridDim,
struct dim3 blockDim,
@@ -1954,38 +1941,33 @@ void print_splash()
}
}
-std::map<const void*,std::string> g_const_name_lookup; // indexed by hostVar
-std::map<const void*,std::string> g_global_name_lookup; // indexed by hostVar
-std::set<std::string> g_globals;
-std::set<std::string> g_constants;
-
-void gpgpu_ptx_sim_register_const_variable(void *hostVar, const char *deviceName, size_t size )
+void cuda_sim::gpgpu_ptx_sim_register_const_variable(void *hostVar, const char *deviceName, size_t size )
{
printf("GPGPU-Sim PTX registering constant %s (%zu bytes) to name mapping\n", deviceName, size );
g_const_name_lookup[hostVar] = deviceName;
}
-void gpgpu_ptx_sim_register_global_variable(void *hostVar, const char *deviceName, size_t size )
+void cuda_sim::gpgpu_ptx_sim_register_global_variable(void *hostVar, const char *deviceName, size_t size )
{
printf("GPGPU-Sim PTX registering global %s hostVar to name mapping\n", deviceName );
g_global_name_lookup[hostVar] = deviceName;
}
-void gpgpu_ptx_sim_memcpy_symbol(const char *hostVar, const void *src, size_t count, size_t offset, int to, gpgpu_t *gpu )
+void cuda_sim::gpgpu_ptx_sim_memcpy_symbol(const char *hostVar, const void *src, size_t count, size_t offset, int to, gpgpu_t *gpu )
{
printf("GPGPU-Sim PTX: starting gpgpu_ptx_sim_memcpy_symbol with hostVar 0x%p\n", hostVar);
bool found_sym = false;
memory_space_t mem_region = undefined_space;
std::string sym_name;
- std::map<const void*,std::string>::iterator c=g_const_name_lookup.find(hostVar);
- if ( c!=g_const_name_lookup.end() ) {
+ std::map<const void*,std::string>::iterator c=gpu->gpgpu_ctx->func_sim->g_const_name_lookup.find(hostVar);
+ if ( c!=gpu->gpgpu_ctx->func_sim->g_const_name_lookup.end() ) {
found_sym = true;
sym_name = c->second;
mem_region = const_space;
}
- std::map<const void*,std::string>::iterator g=g_global_name_lookup.find(hostVar);
- if ( g!=g_global_name_lookup.end() ) {
+ std::map<const void*,std::string>::iterator g=gpu->gpgpu_ctx->func_sim->g_global_name_lookup.find(hostVar);
+ if ( g!=gpu->gpgpu_ctx->func_sim->g_global_name_lookup.end() ) {
if ( found_sym ) {
printf("Execution error: PTX symbol \"%s\" w/ hostVar=0x%Lx is declared both const and global?\n",
sym_name.c_str(), (unsigned long long)hostVar );
@@ -2041,13 +2023,9 @@ void gpgpu_ptx_sim_memcpy_symbol(const char *hostVar, const void *src, size_t co
fflush(stdout);
}
-int g_ptx_sim_mode; // if non-zero run functional simulation only (i.e., no notion of a clock cycle)
-
extern int ptx_debug;
-bool g_cuda_launch_blocking = false;
-
-void read_sim_environment_variables()
+void cuda_sim::read_sim_environment_variables()
{
ptx_debug = 0;
g_debug_execution = 0;
@@ -2105,8 +2083,6 @@ void read_sim_environment_variables()
}
}
-ptx_cta_info *g_func_cta_info = NULL;
-
#define MAX(a,b) (((a)>(b))?(a):(b))
unsigned max_cta (const struct gpgpu_ptx_sim_info *kernel_info, unsigned threads_per_cta, unsigned int warp_size, unsigned int n_thread_per_shader, unsigned int gpgpu_shmem_size, unsigned int gpgpu_shader_registers, unsigned int max_cta_per_core)
@@ -2145,7 +2121,7 @@ unsigned max_cta (const struct gpgpu_ptx_sim_info *kernel_info, unsigned threads
This function simulates the CUDA code functionally, it takes a kernel_info_t parameter
which holds the data for the CUDA kernel to be executed
!*/
-void gpgpu_cuda_ptx_sim_main_func( kernel_info_t &kernel, bool openCL )
+void cuda_sim::gpgpu_cuda_ptx_sim_main_func( kernel_info_t &kernel, bool openCL )
{
printf("GPGPU-Sim: Performing Functional Simulation, executing kernel %s...\n",kernel.name().c_str());
@@ -2195,7 +2171,7 @@ void gpgpu_cuda_ptx_sim_main_func( kernel_info_t &kernel, bool openCL )
cta.execute(cp_count,temp);
#if (CUDART_VERSION >= 5000)
- launch_all_device_kernels();
+ gpgpu_ctx->device_runtime->launch_all_device_kernels();
#endif
}
else
@@ -2271,7 +2247,7 @@ void functionalCoreSim::initializeCTA(unsigned ctaid_cp)
assert(m_thread[i]!=NULL && !m_thread[i]->is_done());
char fname[2048];
snprintf(fname,2048,"checkpoint_files/thread_%d_0_reg.txt",i );
- if(cp_cta_resume==1)
+ if(m_gpu->gpgpu_ctx->func_sim->cp_cta_resume==1)
m_thread[i]->resume_reg_thread(fname,symtab);
ctaLiveThreads++;
}
@@ -2295,7 +2271,7 @@ void functionalCoreSim::createWarp(unsigned warpId)
char fname[2048];
snprintf(fname,2048,"checkpoint_files/warp_%d_0_simt.txt",warpId );
- if(cp_cta_resume==1)
+ if(m_gpu->gpgpu_ctx->func_sim->cp_cta_resume==1)
{
unsigned pc,rpc;
m_simt_stack[warpId]->resume(fname);
@@ -2311,8 +2287,8 @@ void functionalCoreSim::createWarp(unsigned warpId)
void functionalCoreSim::execute(int inst_count, unsigned ctaid_cp)
{
- cp_count= m_gpu->checkpoint_insn_Y;
- cp_cta_resume= m_gpu->checkpoint_CTA_t;
+ m_gpu->gpgpu_ctx->func_sim->cp_count= m_gpu->checkpoint_insn_Y;
+ m_gpu->gpgpu_ctx->func_sim->cp_cta_resume= m_gpu->checkpoint_CTA_t;
initializeCTA(ctaid_cp);
int count=0;
@@ -2405,8 +2381,6 @@ unsigned translate_pc_to_ptxlineno(unsigned pc)
extern std::map<unsigned,const char*> get_duplicate();
-int g_ptxinfo_error_detected;
-
static char *g_ptxinfo_kname = NULL;
static struct gpgpu_ptx_sim_info g_ptxinfo;
static std::map<unsigned,const char*> g_duplicate;
@@ -2534,14 +2508,7 @@ void ptxinfo_opencl_addinfo( std::map<std::string,function_info*> &kernels )
clear_ptxinfo();
}
-struct rec_pts {
- gpgpu_recon_t *s_kernel_recon_points;
- int s_num_recon;
-};
-
-class std::map<function_info*,rec_pts> g_rpts;
-
-struct rec_pts find_reconvergence_points( function_info *finfo )
+struct rec_pts cuda_sim::find_reconvergence_points( function_info *finfo )
{
rec_pts tmp;
std::map<function_info*,rec_pts>::iterator r=g_rpts.find(finfo);
@@ -2580,7 +2547,7 @@ address_type get_return_pc( void *thd )
return the_thread->get_return_PC();
}
-address_type get_converge_point( address_type pc )
+address_type cuda_sim::get_converge_point( address_type pc )
{
// the branch could encode the reconvergence point and/or a bit that indicates the
// reconvergence point is the return PC on the call stack in the case the branch has
diff --git a/src/cuda-sim/cuda-sim.h b/src/cuda-sim/cuda-sim.h
index e690356..e4d34fe 100644
--- a/src/cuda-sim/cuda-sim.h
+++ b/src/cuda-sim/cuda-sim.h
@@ -36,33 +36,16 @@
#include <string>
#include"ptx_sim.h"
+class gpgpu_context;
class memory_space;
class function_info;
class symbol_table;
extern const char *g_gpgpusim_version_string;
-extern int g_ptx_sim_mode;
extern int g_debug_execution;
-extern int g_debug_thread_uid;
-extern void ** g_inst_classification_stat;
-extern void ** g_inst_op_classification_stat;
-extern int g_ptx_kernel_count; // used for classification stat collection purposes
-extern char *opcode_latency_int, *opcode_latency_fp, *opcode_latency_dp,*opcode_latency_sfu,*opcode_latency_tensor;
-
-void ptx_opcocde_latency_options (option_parser_t opp);
-extern class kernel_info_t *gpgpu_opencl_ptx_sim_init_grid(class function_info *entry,
- gpgpu_ptx_sim_arg_list_t args,
- struct dim3 gridDim,
- struct dim3 blockDim,
- class gpgpu_t *gpu );
-extern void gpgpu_cuda_ptx_sim_main_func( kernel_info_t &kernel, bool openCL = false );
extern void print_splash();
-extern void gpgpu_ptx_sim_register_const_variable(void*, const char *deviceName, size_t size );
-extern void gpgpu_ptx_sim_register_global_variable(void *hostVar, const char *deviceName, size_t size );
-extern void gpgpu_ptx_sim_memcpy_symbol(const char *hostVar, const void *src, size_t count, size_t offset, int to, gpgpu_t *gpu );
-extern void read_sim_environment_variables();
extern void ptxinfo_opencl_addinfo( std::map<std::string,function_info*> &kernels );
unsigned ptx_sim_init_thread( kernel_info_t &kernel,
class ptx_thread_info** thread_info,
@@ -77,9 +60,6 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel,
bool functionalSimulationMode = false);
const warp_inst_t *ptx_fetch_inst( address_type pc );
const struct gpgpu_ptx_sim_info* ptx_sim_kernel_info(const class function_info *kernel);
-void ptx_print_insn( address_type pc, FILE *fp );
-std::string ptx_get_insn_str( address_type pc );
-void set_param_gpgpu_num_shaders(int num_shaders);
/*!
@@ -134,4 +114,80 @@ void print_ptxinfo();
void clear_ptxinfo();
struct gpgpu_ptx_sim_info get_ptxinfo();
+class gpgpu_recon_t;
+struct rec_pts {
+ gpgpu_recon_t *s_kernel_recon_points;
+ int s_num_recon;
+};
+
+
+class cuda_sim {
+ public:
+ cuda_sim( gpgpu_context* ctx ) {
+ g_ptx_sim_num_insn = 0;
+ g_ptx_kernel_count = -1; // used for classification stat collection purposes
+ gpgpu_param_num_shaders = 0;
+ g_cuda_launch_blocking = false;
+ g_inst_classification_stat = NULL;
+ g_inst_op_classification_stat= NULL;
+ g_assemble_code_next_pc=0;
+ g_debug_thread_uid = 0;
+ gpgpu_ctx = ctx;
+ }
+ //global variables
+ char *opcode_latency_int;
+ char *opcode_latency_fp;
+ char *opcode_latency_dp;
+ char *opcode_latency_sfu;
+ char *opcode_latency_tensor;
+ char *opcode_initiation_int;
+ char *opcode_initiation_fp;
+ char *opcode_initiation_dp;
+ char *opcode_initiation_sfu;
+ char *opcode_initiation_tensor;
+ int cp_count;
+ int cp_cta_resume;
+ int g_ptxinfo_error_detected;
+ unsigned g_ptx_sim_num_insn;
+ char *cdp_latency_str;
+ int g_ptx_kernel_count; // used for classification stat collection purposes
+ std::map<const void*,std::string> g_global_name_lookup; // indexed by hostVar
+ std::map<const void*,std::string> g_const_name_lookup; // indexed by hostVar
+ int g_ptx_sim_mode; // if non-zero run functional simulation only (i.e., no notion of a clock cycle)
+ unsigned gpgpu_param_num_shaders;
+ class std::map<function_info*,rec_pts> g_rpts;
+ bool g_cuda_launch_blocking;
+ void ** g_inst_classification_stat;
+ void ** g_inst_op_classification_stat;
+ std::set<std::string> g_globals;
+ std::set<std::string> g_constants;
+ std::map<unsigned,function_info*> g_pc_to_finfo;
+ int gpgpu_ptx_instruction_classification;
+ unsigned cdp_latency[5];
+ unsigned g_assemble_code_next_pc;
+ int g_debug_thread_uid;
+ // backward pointer
+ class gpgpu_context* gpgpu_ctx;
+ //global functions
+ void ptx_opcocde_latency_options (option_parser_t opp);
+ void gpgpu_cuda_ptx_sim_main_func( kernel_info_t &kernel, bool openCL = false );
+ int gpgpu_opencl_ptx_sim_main_func( kernel_info_t *grid );
+ void init_inst_classification_stat();
+ kernel_info_t *gpgpu_opencl_ptx_sim_init_grid(class function_info *entry,
+ gpgpu_ptx_sim_arg_list_t args,
+ struct dim3 gridDim,
+ struct dim3 blockDim,
+ gpgpu_t *gpu );
+ void gpgpu_ptx_sim_register_global_variable(void *hostVar, const char *deviceName, size_t size );
+ void gpgpu_ptx_sim_register_const_variable(void*, const char *deviceName, size_t size );
+ void read_sim_environment_variables();
+ void set_param_gpgpu_num_shaders(int num_shaders);
+ struct rec_pts find_reconvergence_points( function_info *finfo );
+ address_type get_converge_point( address_type pc );
+ void gpgpu_ptx_sim_memcpy_symbol(const char *hostVar, const void *src, size_t count, size_t offset, int to, gpgpu_t *gpu );
+ void ptx_print_insn( address_type pc, FILE *fp );
+ std::string ptx_get_insn_str( address_type pc );
+ template<int activate_level> bool ptx_debug_exec_dump_cond(int thd_uid, addr_t pc);
+};
+
#endif
diff --git a/src/cuda-sim/cuda_device_runtime.cc b/src/cuda-sim/cuda_device_runtime.cc
index be8369f..354fa79 100644
--- a/src/cuda-sim/cuda_device_runtime.cc
+++ b/src/cuda-sim/cuda_device_runtime.cc
@@ -20,6 +20,7 @@ unsigned long long g_max_total_param_size = 0;
#include "../stream_manager.h"
#include "../gpgpusim_entrypoint.h"
#include "cuda_device_runtime.h"
+#include "../../libcuda/gpgpu_context.h"
#define DEV_RUNTIME_REPORT(a) \
if( g_debug_execution ) { \
@@ -318,17 +319,17 @@ void gpgpusim_cuda_streamCreateWithFlags(const ptx_instruction * pI, ptx_thread_
}
-void launch_one_device_kernel() {
+void cuda_device_runtime::launch_one_device_kernel() {
if(!g_cuda_device_launch_op.empty()) {
device_launch_operation_t &op = g_cuda_device_launch_op.front();
- stream_operation stream_op = stream_operation(op.grid, g_ptx_sim_mode, op.stream);
+ stream_operation stream_op = stream_operation(op.grid, gpgpu_ctx->func_sim->g_ptx_sim_mode, op.stream);
g_stream_manager()->push(stream_op);
g_cuda_device_launch_op.pop_front();
}
}
-void launch_all_device_kernels() {
+void cuda_device_runtime::launch_all_device_kernels() {
while(!g_cuda_device_launch_op.empty()) {
launch_one_device_kernel();
}
diff --git a/src/cuda-sim/cuda_device_runtime.h b/src/cuda-sim/cuda_device_runtime.h
index 6dbcd71..851fed2 100644
--- a/src/cuda-sim/cuda_device_runtime.h
+++ b/src/cuda-sim/cuda_device_runtime.h
@@ -6,6 +6,20 @@
void gpgpusim_cuda_getParameterBufferV2(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func);
void gpgpusim_cuda_launchDeviceV2(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func);
void gpgpusim_cuda_streamCreateWithFlags(const ptx_instruction * pI, ptx_thread_info * thread, const function_info * target_func);
-void launch_all_device_kernels();
-void launch_one_device_kernel();
+#endif
+#if (CUDART_VERSION >= 5000)
+
+class gpgpu_context;
+
+class cuda_device_runtime {
+ public:
+ cuda_device_runtime( gpgpu_context* ctx ) {
+ gpgpu_ctx = ctx;
+ }
+ // backward pointer
+ class gpgpu_context* gpgpu_ctx;
+ void launch_all_device_kernels();
+ void launch_one_device_kernel();
+};
+
#endif
diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc
index 8cedf79..c537091 100644
--- a/src/cuda-sim/ptx_ir.cc
+++ b/src/cuda-sim/ptx_ir.cc
@@ -83,8 +83,9 @@ symbol_table::symbol_table()
assert(0);
}
-symbol_table::symbol_table( const char *scope_name, unsigned entry_point, symbol_table *parent )
+symbol_table::symbol_table( const char *scope_name, unsigned entry_point, symbol_table *parent, gpgpu_context* ctx )
{
+ gpgpu_ctx = ctx;
m_scope_name = std::string(scope_name);
m_reg_allocator=0;
m_shared_next = 0;
@@ -183,7 +184,7 @@ symbol_table* symbol_table::start_inst_group() {
//previous added
assert(m_inst_group_symtab.find(std::string(inst_group_name)) == m_inst_group_symtab.end());
- symbol_table *sym_table = new symbol_table(inst_group_name, 3/*inst group*/, this );
+ symbol_table *sym_table = new symbol_table(inst_group_name, 3/*inst group*/, this, gpgpu_ctx );
sym_table->m_global_next = m_global_next;
sym_table->m_shared_next = m_shared_next;
@@ -221,7 +222,7 @@ bool symbol_table::add_function_decl( const char *name, int entry_point, functio
*func_info = m_function_info_lookup[key];
prior_decl = true;
} else {
- *func_info = new function_info(entry_point);
+ *func_info = new function_info(entry_point, gpgpu_ctx);
(*func_info)->set_name(name);
(*func_info)->set_maxnt_id(0);
m_function_info_lookup[key] = *func_info;
@@ -232,7 +233,7 @@ bool symbol_table::add_function_decl( const char *name, int entry_point, functio
*sym_table = m_function_symtab_lookup[key];
} else {
assert( !prior_decl );
- *sym_table = new symbol_table( "", entry_point, this );
+ *sym_table = new symbol_table( "", entry_point, this, gpgpu_ctx );
// Initial setup code to support a register represented as "_".
// This register is used when an instruction operand is
@@ -1095,8 +1096,10 @@ ptx_instruction::ptx_instruction( int opcode,
const char *file,
unsigned line,
const char *source,
- const core_config *config ) : warp_inst_t(config)
+ const core_config *config,
+ gpgpu_context* ctx ) : warp_inst_t(config)
{
+ gpgpu_ctx = ctx;
m_uid = ++g_num_ptx_inst_uid;
m_PC = 0;
m_opcode = opcode;
@@ -1371,8 +1374,9 @@ std::string ptx_instruction::to_string() const
unsigned function_info::sm_next_uid = 1;
-function_info::function_info(int entry_point )
+function_info::function_info(int entry_point, gpgpu_context* ctx )
{
+ gpgpu_ctx = ctx;
m_uid = sm_next_uid++;
m_entry_point = (entry_point==1)?true:false;
m_extern = (entry_point==2)?true:false;
diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h
index 1af85de..babd54b 100644
--- a/src/cuda-sim/ptx_ir.h
+++ b/src/cuda-sim/ptx_ir.h
@@ -43,6 +43,8 @@
#include "memory.h"
+class gpgpu_context;
+
class type_info_key {
public:
type_info_key()
@@ -304,7 +306,7 @@ private:
class symbol_table {
public:
symbol_table();
- symbol_table( const char *scope_name, unsigned entry_point, symbol_table *parent );
+ symbol_table( const char *scope_name, unsigned entry_point, symbol_table *parent, gpgpu_context* ctx);
void set_name( const char *name );
const ptx_version &get_ptx_version() const;
unsigned get_sm_target() const;
@@ -346,6 +348,9 @@ public:
symbol_table* start_inst_group();
symbol_table* end_inst_group();
+ // backward pointer
+ class gpgpu_context* gpgpu_ctx;
+
private:
unsigned m_reg_allocator;
unsigned m_shared_next;
@@ -931,7 +936,8 @@ public:
const char *file,
unsigned line,
const char *source,
- const core_config *config );
+ const core_config *config,
+ gpgpu_context* ctx);
void print_insn() const;
virtual void print_insn( FILE *fp ) const;
@@ -1187,6 +1193,8 @@ private:
virtual void pre_decode();
friend class function_info;
static unsigned g_num_ptx_inst_uid;
+ // backward pointer
+ class gpgpu_context* gpgpu_ctx;
};
class param_info {
@@ -1228,7 +1236,7 @@ private:
class function_info {
public:
- function_info(int entry_point );
+ function_info(int entry_point, gpgpu_context* ctx );
const ptx_version &get_ptx_version() const { return m_symtab->get_ptx_version(); }
unsigned get_sm_target() const { return m_symtab->get_sm_target(); }
bool is_extern() const { return m_extern; }
@@ -1398,6 +1406,8 @@ public:
void set_maxnt_id(unsigned maxthreads) { maxnt_id = maxthreads;}
unsigned get_maxnt_id() { return maxnt_id;}
+ // backward pointer
+ class gpgpu_context* gpgpu_ctx;
private:
unsigned maxnt_id;
@@ -1575,11 +1585,8 @@ struct textureInfo {
extern std::map<std::string,symbol_table*> g_sym_name_to_symbol_table;
-extern bool g_keep_intermediate_files;
-
void gpgpu_ptx_assemble( std::string kname, void *kinfo );
#include "../option_parser.h"
-void ptx_reg_options(option_parser_t opp);
unsigned ptx_kernel_shmem_size( void *kernel_impl );
unsigned ptx_kernel_nregs( void *kernel_impl );
diff --git a/src/cuda-sim/ptx_loader.cc b/src/cuda-sim/ptx_loader.cc
index 921d1e6..2bf464c 100644
--- a/src/cuda-sim/ptx_loader.cc
+++ b/src/cuda-sim/ptx_loader.cc
@@ -58,21 +58,19 @@ extern int ptxinfo_lex_destroy(yyscan_t scanner);
static bool g_save_embedded_ptx;
static int g_occupancy_sm_number;
-bool g_keep_intermediate_files;
-bool m_ptx_save_converted_ptxplus;
-bool keep_intermediate_files() {return g_keep_intermediate_files;}
+bool ptxinfo_data::keep_intermediate_files() {return g_keep_intermediate_files;}
-void ptx_reg_options(option_parser_t opp)
+void gpgpu_context::ptx_reg_options(option_parser_t opp)
{
option_parser_register(opp, "-save_embedded_ptx", OPT_BOOL, &g_save_embedded_ptx,
"saves ptx files embedded in binary as <n>.ptx",
"0");
- option_parser_register(opp, "-keep", OPT_BOOL, &g_keep_intermediate_files,
+ option_parser_register(opp, "-keep", OPT_BOOL, &(ptxinfo->g_keep_intermediate_files),
"keep intermediate files created by GPGPU-Sim when interfacing with external programs",
"0");
option_parser_register(opp, "-gpgpu_ptx_save_converted_ptxplus", OPT_BOOL,
- &m_ptx_save_converted_ptxplus,
+ &(ptxinfo->m_ptx_save_converted_ptxplus),
"Saved converted ptxplus to a file",
"0");
option_parser_register(opp, "-gpgpu_occupancy_sm_number", OPT_INT32, &g_occupancy_sm_number,
@@ -107,7 +105,7 @@ void gpgpu_context::print_ptx_file( const char *p, unsigned source_num, const ch
fflush(stdout);
}
-char* gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus(const std::string ptxfilename, const std::string elffilename, const std::string sassfilename)
+char* ptxinfo_data::gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus(const std::string ptxfilename, const std::string elffilename, const std::string sassfilename)
{
printf("GPGPU-Sim PTX: converting EMBEDDED .ptx file to ptxplus \n");
diff --git a/src/cuda-sim/ptx_loader.h b/src/cuda-sim/ptx_loader.h
index c214b95..decfdc8 100644
--- a/src/cuda-sim/ptx_loader.h
+++ b/src/cuda-sim/ptx_loader.h
@@ -42,14 +42,15 @@ class ptxinfo_data{
unsigned col;
const char *g_ptxinfo_filename;
class gpgpu_context* gpgpu_ctx;
+ bool g_keep_intermediate_files;
+ bool m_ptx_save_converted_ptxplus;
void ptxinfo_addinfo();
+ bool keep_intermediate_files();
+ char* gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus(const std::string ptx_str, const std::string sass_str, const std::string elf_str);
};
extern bool g_override_embedded_ptx;
extern int no_of_ptx; //counter to track number of ptx files to be extracted in an application.
-char* gpgpu_ptx_sim_convert_ptx_and_sass_to_ptxplus(const std::string ptx_str, const std::string sass_str, const std::string elf_str);
-bool keep_intermediate_files();
-
#endif
diff --git a/src/cuda-sim/ptx_parser.cc b/src/cuda-sim/ptx_parser.cc
index 05fc618..5a94679 100644
--- a/src/cuda-sim/ptx_parser.cc
+++ b/src/cuda-sim/ptx_parser.cc
@@ -112,7 +112,7 @@ symbol_table * gpgpu_context::init_parser( const char *ptx_filename )
{
g_filename = strdup(ptx_filename);
if (g_global_allfiles_symbol_table == NULL) {
- g_global_allfiles_symbol_table = new symbol_table("global_allfiles", 0, NULL);
+ g_global_allfiles_symbol_table = new symbol_table("global_allfiles", 0, NULL, this);
ptx_parser->g_global_symbol_table = ptx_parser->g_current_symbol_table = g_global_allfiles_symbol_table;
}
/*else {
@@ -285,7 +285,8 @@ void ptx_recognizer::add_instruction()
gpgpu_ctx->g_filename,
ptx_get_lineno(scanner),
linebuf,
- g_shader_core_config );
+ g_shader_core_config,
+ gpgpu_ctx );
g_instructions.push_back(i);
g_inst_lookup[gpgpu_ctx->g_filename][ptx_get_lineno(scanner)] = i;
init_instruction_state();
@@ -321,9 +322,6 @@ bool ptx_recognizer::check_for_duplicates( const char *identifier )
return ( s != NULL );
}
-extern std::set<std::string> g_globals;
-extern std::set<std::string> g_constants;
-
// Returns padding that needs to be inserted ahead of address to make it aligned to min(size, maxalign)
/*
* @param address the address in bytes
@@ -452,7 +450,7 @@ void ptx_recognizer::add_identifier( const char *identifier, int array_dim, unsi
g_current_symbol_table->alloc_global( num_bits/8 + addr_pad );
}
if( g_current_symbol_table == g_global_symbol_table ) {
- g_constants.insert( identifier );
+ gpgpu_ctx->func_sim->g_constants.insert( identifier );
}
assert( g_current_symbol_table != NULL );
g_sym_name_to_symbol_table[ identifier ] = g_current_symbol_table;
@@ -470,7 +468,7 @@ void ptx_recognizer::add_identifier( const char *identifier, int array_dim, unsi
fflush(stdout);
g_last_symbol->set_address( addr+addr_pad );
g_current_symbol_table->alloc_global( num_bits/8 + addr_pad );
- g_globals.insert( identifier );
+ gpgpu_ctx->func_sim->g_globals.insert( identifier );
assert( g_current_symbol_table != NULL );
g_sym_name_to_symbol_table[ identifier ] = g_current_symbol_table;
break;
diff --git a/src/cuda-sim/ptx_parser.h b/src/cuda-sim/ptx_parser.h
index e09aab1..ef422e5 100644
--- a/src/cuda-sim/ptx_parser.h
+++ b/src/cuda-sim/ptx_parser.h
@@ -30,7 +30,6 @@
#include "../abstract_hardware_model.h"
#include "ptx_ir.h"
-extern int g_error_detected;
#ifdef __cplusplus
const class ptx_instruction *ptx_instruction_lookup( const char *filename, unsigned linenumber );
diff --git a/src/cuda-sim/ptxinfo.l b/src/cuda-sim/ptxinfo.l
index 3a152b0..51371e3 100644
--- a/src/cuda-sim/ptxinfo.l
+++ b/src/cuda-sim/ptxinfo.l
@@ -88,13 +88,11 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
%%
-extern int g_ptxinfo_error_detected;
-
int ptxinfo_error(yyscan_t yyscanner, ptxinfo_data* ptxinfo, const char* msg)
{
struct yyguts_t * yyg = (struct yyguts_t*)yyscanner;
int i;
- g_ptxinfo_error_detected = 1;
+ ptxinfo->gpgpu_ctx->func_sim->g_ptxinfo_error_detected = 1;
fflush(stdout);
printf("GPGPU-Sim: ERROR while parsing output of ptxas (used to capture resource usage information)\n");
if( msg != NULL )
diff --git a/src/debug.h b/src/debug.h
index 1277494..1005bd5 100644
--- a/src/debug.h
+++ b/src/debug.h
@@ -83,8 +83,6 @@ private:
unsigned m_value;
};
-extern int gpgpu_ptx_instruction_classification ;
-
class ptx_thread_info;
class ptx_instruction;
bool thread_at_brkpt( ptx_thread_info *thd_info, const class brk_pt &b );
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 2ff37d1..93f041a 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -499,11 +499,11 @@ void gpgpu_sim_config::reg_options(option_parser_t opp)
option_parser_register(opp, "-gpgpu_deadlock_detect", OPT_BOOL, &gpu_deadlock_detect,
"Stop the simulation at deadlock (1=on (default), 0=off)",
"1");
- option_parser_register(opp, "-gpgpu_ptx_instruction_classification", OPT_INT32,
- &gpgpu_ptx_instruction_classification,
+ option_parser_register(opp, "-gpgpu_ptx_instruction_classification", OPT_INT32,
+ &(gpgpu_ctx->func_sim->gpgpu_ptx_instruction_classification),
"if enabled will classify ptx instruction types per kernel (Max 255 kernels now)",
"0");
- option_parser_register(opp, "-gpgpu_ptx_sim_mode", OPT_INT32, &g_ptx_sim_mode,
+ option_parser_register(opp, "-gpgpu_ptx_sim_mode", OPT_INT32, &(gpgpu_ctx->func_sim->g_ptx_sim_mode),
"Select between Performance (default) or Functional simulation (1)",
"0");
option_parser_register(opp, "-gpgpu_clock_domains", OPT_CSTR, &gpgpu_clock_domains,
@@ -699,7 +699,7 @@ void gpgpu_sim::stop_all_running_kernels(){
}
gpgpu_sim::gpgpu_sim( const gpgpu_sim_config &config, gpgpu_context* ctx )
- : gpgpu_t(config), m_config(config)
+ : gpgpu_t(config, ctx), m_config(config)
{
gpgpu_ctx = ctx;
m_shader_config = &m_config.m_shader_config;
@@ -882,7 +882,7 @@ void gpgpu_sim::init()
gpu_sim_cycle_parition_util = 0;
reinit_clock_domains();
- set_param_gpgpu_num_shaders(m_config.num_shader());
+ gpgpu_ctx->func_sim->set_param_gpgpu_num_shaders(m_config.num_shader());
for (unsigned i=0;i<m_shader_config->n_simt_clusters;i++)
m_cluster[i]->reinit();
m_shader_stats->new_grid();
@@ -1200,9 +1200,9 @@ void gpgpu_sim::gpu_print_stat()
spill_log_to_file (stdout, 1, gpu_sim_cycle);
insn_warp_occ_print(stdout);
}
- if ( gpgpu_ptx_instruction_classification ) {
- StatDisp( g_inst_classification_stat[g_ptx_kernel_count]);
- StatDisp( g_inst_op_classification_stat[g_ptx_kernel_count]);
+ if ( gpgpu_ctx->func_sim->gpgpu_ptx_instruction_classification ) {
+ StatDisp( gpgpu_ctx->func_sim->g_inst_classification_stat[gpgpu_ctx->func_sim->g_ptx_kernel_count]);
+ StatDisp( gpgpu_ctx->func_sim->g_inst_op_classification_stat[gpgpu_ctx->func_sim->g_ptx_kernel_count]);
}
#ifdef GPGPUSIM_POWER_MODEL
@@ -1753,7 +1753,7 @@ void gpgpu_sim::cycle()
#if (CUDART_VERSION >= 5000)
//launch device kernel
- launch_one_device_kernel();
+ gpgpu_ctx->device_runtime->launch_one_device_kernel();
#endif
}
}
@@ -1826,7 +1826,7 @@ void gpgpu_sim::dump_pipeline( int mask, int s, int m ) const
fflush(stdout);
}
-const struct shader_core_config * gpgpu_sim::getShaderCoreConfig()
+const shader_core_config * gpgpu_sim::getShaderCoreConfig()
{
return m_shader_config;
}
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index e2c913a..119b934 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -62,6 +62,8 @@
#define SAMPLELOG 222
#define DUMPLOG 333
+class gpgpu_context;
+
extern tr1_hash_map<new_addr_type,unsigned> address_random_interleaving;
enum dram_ctrl_t {
@@ -295,7 +297,10 @@ extern bool g_interactive_debugger_enabled;
class gpgpu_sim_config : public power_config, public gpgpu_functional_sim_config {
public:
- gpgpu_sim_config() { m_valid = false; }
+ gpgpu_sim_config(gpgpu_context* ctx): m_shader_config(ctx) {
+ m_valid = false;
+ gpgpu_ctx = ctx;
+ }
void reg_options(class OptionParser * opp);
void init()
{
@@ -341,6 +346,8 @@ private:
void init_clock_domains(void );
+ // backward pointer
+ class gpgpu_context* gpgpu_ctx;
bool m_valid;
shader_core_config m_shader_config;
memory_config m_memory_config;
@@ -473,7 +480,7 @@ public:
/*!
* Returning the configuration of the shader core, used by the functional simulation only so far
*/
- const struct shader_core_config * getShaderCoreConfig();
+ const shader_core_config * getShaderCoreConfig();
//! Get shader core Memory Configuration
@@ -489,6 +496,8 @@ public:
*/
simt_core_cluster * getSIMTCluster();
+ // backward pointer
+ class gpgpu_context* gpgpu_ctx;
private:
// clocks
@@ -506,8 +515,6 @@ private:
void gpgpu_debug();
///// data /////
-// backward pointer
- class gpgpu_context* gpgpu_ctx;
class simt_core_cluster **m_cluster;
class memory_partition_unit **m_memory_partition_unit;
@@ -537,7 +544,7 @@ private:
const gpgpu_sim_config &m_config;
const struct cudaDeviceProp *m_cuda_properties;
- const struct shader_core_config *m_shader_config;
+ const shader_core_config *m_shader_config;
const struct memory_config *m_memory_config;
// stats
diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc
index 04dc75b..d08ba39 100644
--- a/src/gpgpu-sim/mem_latency_stat.cc
+++ b/src/gpgpu-sim/mem_latency_stat.cc
@@ -42,7 +42,7 @@
#include <stdlib.h>
#include <stdio.h>
-memory_stats_t::memory_stats_t( unsigned n_shader, const struct shader_core_config *shader_config, const struct memory_config *mem_config, const class gpgpu_sim* gpu )
+memory_stats_t::memory_stats_t( unsigned n_shader, const shader_core_config *shader_config, const struct memory_config *mem_config, const class gpgpu_sim* gpu )
{
assert( mem_config->m_valid );
assert( shader_config->m_valid );
diff --git a/src/gpgpu-sim/mem_latency_stat.h b/src/gpgpu-sim/mem_latency_stat.h
index b9285c1..6ce568d 100644
--- a/src/gpgpu-sim/mem_latency_stat.h
+++ b/src/gpgpu-sim/mem_latency_stat.h
@@ -35,7 +35,7 @@
class memory_stats_t {
public:
memory_stats_t( unsigned n_shader,
- const struct shader_core_config *shader_config,
+ const class shader_core_config *shader_config,
const struct memory_config *mem_config,
const class gpgpu_sim* gpu);
@@ -53,7 +53,7 @@ public:
unsigned m_n_shader;
- const struct shader_core_config *m_shader_config;
+ const shader_core_config *m_shader_config;
const struct memory_config *m_memory_config;
const class gpgpu_sim* m_gpu;
diff --git a/src/gpgpu-sim/power_interface.cc b/src/gpgpu-sim/power_interface.cc
index 3861b6a..0272aa6 100644
--- a/src/gpgpu-sim/power_interface.cc
+++ b/src/gpgpu-sim/power_interface.cc
@@ -38,7 +38,7 @@ void init_mcpat(const gpgpu_sim_config &config, class gpgpu_sim_wrapper *wrapper
}
-void mcpat_cycle(const gpgpu_sim_config &config, const struct shader_core_config *shdr_config, class gpgpu_sim_wrapper *wrapper, class power_stat_t *power_stats, unsigned stat_sample_freq, unsigned tot_cycle, unsigned cycle, unsigned tot_inst, unsigned inst){
+void mcpat_cycle(const gpgpu_sim_config &config, const shader_core_config *shdr_config, class gpgpu_sim_wrapper *wrapper, class power_stat_t *power_stats, unsigned stat_sample_freq, unsigned tot_cycle, unsigned cycle, unsigned tot_inst, unsigned inst){
static bool mcpat_init=true;
diff --git a/src/gpgpu-sim/power_interface.h b/src/gpgpu-sim/power_interface.h
index afac22b..a388c23 100644
--- a/src/gpgpu-sim/power_interface.h
+++ b/src/gpgpu-sim/power_interface.h
@@ -36,7 +36,7 @@
#include "gpgpu_sim_wrapper.h"
void init_mcpat(const gpgpu_sim_config &config, class gpgpu_sim_wrapper *wrapper, unsigned stat_sample_freq, unsigned tot_inst, unsigned inst);
-void mcpat_cycle(const gpgpu_sim_config &config, const struct shader_core_config *shdr_config, class gpgpu_sim_wrapper *wrapper, class power_stat_t *power_stats,
+void mcpat_cycle(const gpgpu_sim_config &config, const shader_core_config *shdr_config, class gpgpu_sim_wrapper *wrapper, class power_stat_t *power_stats,
unsigned stat_sample_freq, unsigned tot_cycle, unsigned cycle, unsigned tot_inst, unsigned inst);
void mcpat_reset_perf_count(class gpgpu_sim_wrapper *wrapper);
diff --git a/src/gpgpu-sim/power_stat.cc b/src/gpgpu-sim/power_stat.cc
index 4c995e9..007b4c6 100644
--- a/src/gpgpu-sim/power_stat.cc
+++ b/src/gpgpu-sim/power_stat.cc
@@ -42,7 +42,7 @@
-power_mem_stat_t::power_mem_stat_t(const struct memory_config *mem_config, const struct shader_core_config *shdr_config, memory_stats_t *mem_stats, shader_core_stats *shdr_stats){
+power_mem_stat_t::power_mem_stat_t(const struct memory_config *mem_config, const shader_core_config *shdr_config, memory_stats_t *mem_stats, shader_core_stats *shdr_stats){
assert( mem_config->m_valid );
m_mem_stats = mem_stats;
m_config = mem_config;
@@ -125,7 +125,7 @@ void power_mem_stat_t::print (FILE *fout) const {
}
-power_core_stat_t::power_core_stat_t( const struct shader_core_config *shader_config, shader_core_stats *core_stats )
+power_core_stat_t::power_core_stat_t( const shader_core_config *shader_config, shader_core_stats *core_stats )
{
assert( shader_config->m_valid );
m_config = shader_config;
@@ -266,7 +266,7 @@ for(unsigned i=0; i<m_config->num_shader(); ++i){
}
}
-power_stat_t::power_stat_t( const struct shader_core_config *shader_config,float * average_pipeline_duty_cycle,float *active_sms,shader_core_stats * shader_stats, const struct memory_config *mem_config,memory_stats_t * memory_stats)
+power_stat_t::power_stat_t( const shader_core_config *shader_config,float * average_pipeline_duty_cycle,float *active_sms,shader_core_stats * shader_stats, const struct memory_config *mem_config,memory_stats_t * memory_stats)
{
assert( shader_config->m_valid );
assert( mem_config->m_valid );
diff --git a/src/gpgpu-sim/power_stat.h b/src/gpgpu-sim/power_stat.h
index 20af2e5..91fade9 100644
--- a/src/gpgpu-sim/power_stat.h
+++ b/src/gpgpu-sim/power_stat.h
@@ -73,7 +73,7 @@ struct shader_core_power_stats_pod {
class power_core_stat_t : public shader_core_power_stats_pod {
public:
- power_core_stat_t(const struct shader_core_config *shader_config, shader_core_stats *core_stats);
+ power_core_stat_t(const shader_core_config *shader_config, shader_core_stats *core_stats);
void visualizer_print( gzFile visualizer_file );
void print (FILE *fout);
void init();
@@ -113,7 +113,7 @@ struct mem_power_stats_pod{
class power_mem_stat_t : public mem_power_stats_pod{
public:
- power_mem_stat_t(const struct memory_config *mem_config, const struct shader_core_config *shdr_config, memory_stats_t *mem_stats, shader_core_stats *shdr_stats);
+ power_mem_stat_t(const struct memory_config *mem_config, const shader_core_config *shdr_config, memory_stats_t *mem_stats, shader_core_stats *shdr_stats);
void visualizer_print( gzFile visualizer_file );
void print (FILE *fout) const;
void init();
@@ -128,7 +128,7 @@ private:
class power_stat_t {
public:
- power_stat_t( const struct shader_core_config *shader_config,float * average_pipeline_duty_cycle,float * active_sms,shader_core_stats * shader_stats, const struct memory_config *mem_config,memory_stats_t * memory_stats);
+ power_stat_t( const shader_core_config *shader_config,float * average_pipeline_duty_cycle,float * active_sms,shader_core_stats * shader_stats, const struct memory_config *mem_config,memory_stats_t * memory_stats);
void visualizer_print( gzFile visualizer_file );
void print (FILE *fout) const;
void save_stats(){
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index 69b619a..f380560 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -46,6 +46,7 @@
#include <limits.h>
#include "traffic_breakdown.h"
#include "shader_trace.h"
+#include "../../libcuda/gpgpu_context.h"
#define PRIORITIZE_MSHR_OVER_WB 1
#define MAX(a,b) (((a)>(b))?(a):(b))
@@ -69,7 +70,7 @@ shader_core_ctx::shader_core_ctx( class gpgpu_sim *gpu,
class simt_core_cluster *cluster,
unsigned shader_id,
unsigned tpc_id,
- const struct shader_core_config *config,
+ const shader_core_config *config,
const struct memory_config *mem_config,
shader_core_stats *stats )
: core_t( gpu, NULL, config->warp_size, config->n_thread_per_shader ),
@@ -1024,7 +1025,7 @@ void scheduler_unit::cycle()
m_simt_stack[warp_id]->get_pdom_stack_top_info(&pc,&rpc);
SCHED_DPRINTF( "Warp (warp_id %u, dynamic_warp_id %u) has valid instruction (%s)\n",
(*iter)->get_warp_id(), (*iter)->get_dynamic_warp_id(),
- ptx_get_insn_str( pc).c_str() );
+ m_shader->m_config->gpgpu_ctx->func_sim->ptx_get_insn_str( pc).c_str() );
if( pI ) {
assert(valid);
if( pc != pI->pc ) {
@@ -1083,12 +1084,11 @@ void scheduler_unit::cycle()
if(pI->m_is_cdp && !warp(warp_id).m_cdp_dummy) {
assert(warp(warp_id).m_cdp_latency == 0);
- extern unsigned cdp_latency[5];
if(pI->m_is_cdp == 1)
- warp(warp_id).m_cdp_latency = cdp_latency[pI->m_is_cdp - 1];
+ warp(warp_id).m_cdp_latency = m_shader->m_config->gpgpu_ctx->func_sim->cdp_latency[pI->m_is_cdp - 1];
else //cudaLaunchDeviceV2 and cudaGetParameterBufferV2
- warp(warp_id).m_cdp_latency = cdp_latency[pI->m_is_cdp - 1]
- + cdp_latency[pI->m_is_cdp] * active_mask.count();
+ warp(warp_id).m_cdp_latency = m_shader->m_config->gpgpu_ctx->func_sim->cdp_latency[pI->m_is_cdp - 1]
+ + m_shader->m_config->gpgpu_ctx->func_sim->cdp_latency[pI->m_is_cdp] * active_mask.count();
warp(warp_id).m_cdp_dummy = true;
break;
}
@@ -2689,7 +2689,7 @@ void warp_inst_t::print( FILE *fout ) const
for (unsigned j=0; j<m_config->warp_size; j++)
fprintf(fout, "%c", (active(j)?'1':'0') );
fprintf(fout, "]: ");
- ptx_print_insn( pc, fout );
+ m_config->gpgpu_ctx->func_sim->ptx_print_insn( pc, fout );
fprintf(fout, "\n");
}
void shader_core_ctx::incexecstat(warp_inst_t *&inst)
@@ -3018,18 +3018,18 @@ void shader_core_config::set_pipeline_latency() {
* [3] MAD
* [4] DIV
*/
- sscanf(opcode_latency_int, "%u,%u,%u,%u,%u",
+ sscanf(gpgpu_ctx->func_sim->opcode_latency_int, "%u,%u,%u,%u,%u",
&int_latency[0],&int_latency[1],&int_latency[2],
&int_latency[3],&int_latency[4]);
- sscanf(opcode_latency_fp, "%u,%u,%u,%u,%u",
+ sscanf(gpgpu_ctx->func_sim->opcode_latency_fp, "%u,%u,%u,%u,%u",
&fp_latency[0],&fp_latency[1],&fp_latency[2],
&fp_latency[3],&fp_latency[4]);
- sscanf(opcode_latency_dp, "%u,%u,%u,%u,%u",
+ sscanf(gpgpu_ctx->func_sim->opcode_latency_dp, "%u,%u,%u,%u,%u",
&dp_latency[0],&dp_latency[1],&dp_latency[2],
&dp_latency[3],&dp_latency[4]);
- sscanf(opcode_latency_sfu, "%u",
+ sscanf(gpgpu_ctx->func_sim->opcode_latency_sfu, "%u",
&sfu_latency);
- sscanf(opcode_latency_tensor, "%u",
+ sscanf(gpgpu_ctx->func_sim->opcode_latency_tensor, "%u",
&tensor_latency);
//all div operation are executed on sfu
@@ -3786,7 +3786,7 @@ void opndcoll_rfu_t::collector_unit_t::dispatch()
simt_core_cluster::simt_core_cluster( class gpgpu_sim *gpu,
unsigned cluster_id,
- const struct shader_core_config *config,
+ const shader_core_config *config,
const struct memory_config *mem_config,
shader_core_stats *stats,
class memory_stats_t *mstats )
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index 25b9607..2837f1b 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -69,6 +69,8 @@
#define WRITE_MASK_SIZE 8
+class gpgpu_context;
+
enum exec_unit_type_t
{
NONE = 0,
@@ -294,7 +296,7 @@ typedef std::bitset<WARP_PER_CTA_MAX> warp_set_t;
int register_bank(int regnum, int wid, unsigned num_banks, unsigned bank_warp_shift, bool sub_core_model, unsigned banks_per_sched, unsigned sched_id );
class shader_core_ctx;
-struct shader_core_config;
+class shader_core_config;
class shader_core_stats;
enum scheduler_prioritization_type
@@ -1032,7 +1034,7 @@ struct ifetch_buffer_t {
unsigned m_warp_id;
};
-struct shader_core_config;
+class shader_core_config;
class simd_function_unit {
public:
@@ -1362,10 +1364,12 @@ const char* const pipeline_stage_name_decode[] = {
"N_PIPELINE_STAGES"
};
-struct shader_core_config : public core_config
+class shader_core_config : public core_config
{
- shader_core_config(){
+ public:
+ shader_core_config(gpgpu_context* ctx):core_config(ctx){
pipeline_widths_string = NULL;
+ gpgpu_ctx = ctx;
}
void init()
@@ -1425,6 +1429,8 @@ struct shader_core_config : public core_config
unsigned cid_to_sid( unsigned cid, unsigned cluster_id ) const { return cluster_id*n_simt_cores_per_cluster + cid; }
void set_pipeline_latency();
+ // backward pointer
+ class gpgpu_context* gpgpu_ctx;
// data
char *gpgpu_shader_core_pipeline_opt;
bool gpgpu_perfect_mem;
@@ -1770,7 +1776,7 @@ public:
class simt_core_cluster *cluster,
unsigned shader_id,
unsigned tpc_id,
- const struct shader_core_config *config,
+ const shader_core_config *config,
const struct memory_config *mem_config,
shader_core_stats *stats );
@@ -2065,7 +2071,7 @@ class simt_core_cluster {
public:
simt_core_cluster( class gpgpu_sim *gpu,
unsigned cluster_id,
- const struct shader_core_config *config,
+ const shader_core_config *config,
const struct memory_config *mem_config,
shader_core_stats *stats,
memory_stats_t *mstats );
diff --git a/src/gpgpusim_entrypoint.cc b/src/gpgpusim_entrypoint.cc
index b54f20c..816159f 100644
--- a/src/gpgpusim_entrypoint.cc
+++ b/src/gpgpusim_entrypoint.cc
@@ -134,7 +134,7 @@ void *gpgpu_sim_thread_concurrent(void*)
if( GPGPUsim_ctx_ptr()->g_the_gpu->is_functional_sim()) {
kernel_info_t * kernel = GPGPUsim_ctx_ptr()->g_the_gpu->get_functional_kernel();
assert(kernel);
- gpgpu_cuda_ptx_sim_main_func(*kernel);
+ GPGPUsim_ctx_ptr()->gpgpu_ctx->func_sim->gpgpu_cuda_ptx_sim_main_func(*kernel);
GPGPUsim_ctx_ptr()->g_the_gpu->finish_functional_sim(kernel);
}
@@ -207,21 +207,19 @@ void exit_simulation()
fflush(stdout);
}
-extern bool g_cuda_launch_blocking;
-
gpgpu_sim *gpgpu_context::gpgpu_ptx_sim_init_perf()
{
srand(1);
print_splash();
- read_sim_environment_variables();
+ func_sim->read_sim_environment_variables();
ptx_parser->read_parser_environment_variables();
option_parser_t opp = option_parser_create();
ptx_reg_options(opp);
- ptx_opcocde_latency_options(opp);
+ func_sim->ptx_opcocde_latency_options(opp);
icnt_reg_options(opp);
- GPGPUsim_ctx_ptr()->g_the_gpu_config = new gpgpu_sim_config();
+ GPGPUsim_ctx_ptr()->g_the_gpu_config = new gpgpu_sim_config(this);
GPGPUsim_ctx_ptr()->g_the_gpu_config->reg_options(opp); // register GPU microrachitecture options
option_parser_cmdline(opp, sg_argc, sg_argv); // parse configuration options
@@ -233,7 +231,7 @@ gpgpu_sim *gpgpu_context::gpgpu_ptx_sim_init_perf()
GPGPUsim_ctx_ptr()->g_the_gpu_config->init();
GPGPUsim_ctx_ptr()->g_the_gpu = new gpgpu_sim(*(GPGPUsim_ctx_ptr()->g_the_gpu_config), this);
- GPGPUsim_ctx_ptr()->g_stream_manager = new stream_manager((GPGPUsim_ctx_ptr()->g_the_gpu),g_cuda_launch_blocking);
+ GPGPUsim_ctx_ptr()->g_stream_manager = new stream_manager((GPGPUsim_ctx_ptr()->g_the_gpu), func_sim->g_cuda_launch_blocking);
GPGPUsim_ctx_ptr()->g_simulation_starttime = time((time_t *)NULL);
@@ -287,7 +285,7 @@ int gpgpu_opencl_ptx_sim_main_perf( kernel_info_t *grid )
/*!
* This function call the CUDA PTX functional simulator
*/
-int gpgpu_opencl_ptx_sim_main_func( kernel_info_t *grid )
+int cuda_sim::gpgpu_opencl_ptx_sim_main_func( kernel_info_t *grid )
{
//calling the CUDA PTX simulator, sending the kernel by reference and a flag set to true,
//the flag used by the function to distinguish OpenCL calls from the CUDA simulation calls which
diff --git a/src/gpgpusim_entrypoint.h b/src/gpgpusim_entrypoint.h
index dfb82d0..887b3c8 100644
--- a/src/gpgpusim_entrypoint.h
+++ b/src/gpgpusim_entrypoint.h
@@ -83,6 +83,5 @@ struct GPGPUsim_ctx* GPGPUsim_ctx_ptr();
class stream_manager* g_stream_manager();
int gpgpu_opencl_ptx_sim_main_perf( kernel_info_t *grid );
-int gpgpu_opencl_ptx_sim_main_func( kernel_info_t *grid );
#endif
diff --git a/src/stream_manager.cc b/src/stream_manager.cc
index e07f4e4..be3dd71 100644
--- a/src/stream_manager.cc
+++ b/src/stream_manager.cc
@@ -29,6 +29,7 @@
#include "gpgpusim_entrypoint.h"
#include "cuda-sim/cuda-sim.h"
#include "gpgpu-sim/gpu-sim.h"
+#include "../libcuda/gpgpu_context.h"
unsigned CUstream_st::sm_next_stream_uid = 0;
@@ -150,13 +151,13 @@ bool stream_operation::do_operation( gpgpu_sim *gpu )
case stream_memcpy_to_symbol:
if(g_debug_execution >= 3)
printf("memcpy to symbol\n");
- gpgpu_ptx_sim_memcpy_symbol(m_symbol,m_host_address_src,m_cnt,m_offset,1,gpu);
+ gpu->gpgpu_ctx->func_sim->gpgpu_ptx_sim_memcpy_symbol(m_symbol,m_host_address_src,m_cnt,m_offset,1,gpu);
m_stream->record_next_done();
break;
case stream_memcpy_from_symbol:
if(g_debug_execution >= 3)
printf("memcpy from symbol\n");
- gpgpu_ptx_sim_memcpy_symbol(m_symbol,m_host_address_dst,m_cnt,m_offset,0,gpu);
+ gpu->gpgpu_ctx->func_sim->gpgpu_ptx_sim_memcpy_symbol(m_symbol,m_host_address_dst,m_cnt,m_offset,0,gpu);
m_stream->record_next_done();
break;
case stream_kernel_launch:
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 06:22:01 +0000