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-rw-r--r--src/abstract_hardware_model.cc22
-rw-r--r--src/abstract_hardware_model.h2
-rw-r--r--src/gpgpu-sim/gpu-cache.cc14
-rw-r--r--src/gpgpu-sim/gpu-cache.h7
-rw-r--r--src/gpgpu-sim/gpu-sim.cc5
-rw-r--r--src/gpgpu-sim/l2cache.cc61
-rw-r--r--src/gpgpu-sim/mem_latency_stat.cc9
-rw-r--r--src/gpgpu-sim/mem_latency_stat.h17
8 files changed, 114 insertions, 23 deletions
diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index cb6f141..5ef7599 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -108,6 +108,28 @@ address_type line_size_based_tag_func(new_addr_type address, new_addr_type line_
return address & ~(line_size-1);
}
+const char * mem_access_type_str(enum mem_access_type access_type)
+{
+ static const char * access_type_str[] = {
+ "GLOBAL_ACC_R",
+ "LOCAL_ACC_R",
+ "CONST_ACC_R",
+ "TEXTURE_ACC_R",
+ "GLOBAL_ACC_W",
+ "LOCAL_ACC_W",
+ "L1_WRBK_ACC",
+ "L2_WRBK_ACC",
+ "INST_ACC_R",
+ "L2_WR_ALLOC_R"
+ };
+
+ assert(sizeof(access_type_str) / sizeof(const char*) == NUM_MEM_ACCESS_TYPE);
+ assert(access_type < NUM_MEM_ACCESS_TYPE);
+
+ return access_type_str[access_type];
+}
+
+
void warp_inst_t::clear_active( const active_mask_t &inactive ) {
active_mask_t test = m_warp_active_mask;
test &= inactive;
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index ce428da..de6eef8 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -540,6 +540,8 @@ enum mem_access_type {
NUM_MEM_ACCESS_TYPE
};
+const char * mem_access_type_str(enum mem_access_type access_type);
+
enum cache_operator_type {
CACHE_UNDEFINED,
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index a687965..d5856aa 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -29,6 +29,20 @@
#include "stat-tool.h"
#include <assert.h>
+const char * cache_request_status_str(enum cache_request_status status)
+{
+ static const char * static_cache_request_status_str[] = {
+ "HIT",
+ "HIT_RESERVED",
+ "MISS",
+ "RESERVATION_FAIL"
+ };
+
+ assert(sizeof(static_cache_request_status_str) / sizeof(const char*) == NUM_CACHE_REQUEST_STATUS);
+ assert(status < NUM_CACHE_REQUEST_STATUS);
+
+ return static_cache_request_status_str[status];
+}
void l2_cache_config::init(linear_to_raw_address_translation *address_mapping){
cache_config::init();
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index 65183e4..4910ca2 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -45,10 +45,11 @@ enum cache_block_state {
};
enum cache_request_status {
- HIT,
+ HIT = 0,
HIT_RESERVED,
MISS,
- RESERVATION_FAIL
+ RESERVATION_FAIL,
+ NUM_CACHE_REQUEST_STATUS
};
enum cache_event {
@@ -57,6 +58,8 @@ enum cache_event {
WRITE_REQUEST_SENT
};
+const char * cache_request_status_str(enum cache_request_status status);
+
struct cache_block_t {
cache_block_t()
{
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index c1f58bf..5dba54b 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -800,11 +800,12 @@ void gpgpu_sim::gpu_print_stat()
// performance counter that are not local to one shader
m_memory_stats->memlatstat_print(m_memory_config->m_n_mem,m_memory_config->nbk);
- m_memory_stats->print(stdout);
for (unsigned i=0;i<m_memory_config->m_n_mem;i++)
m_memory_partition_unit[i]->print(stdout);
- if (!m_memory_config->m_L2_config.disabled() && m_memory_config->m_L2_config.get_num_lines())
+ if (!m_memory_config->m_L2_config.disabled() && m_memory_config->m_L2_config.get_num_lines()) {
L2c_print_cache_stat();
+ m_memory_stats->print_L2cache_stats(stdout);
+ }
if (m_config.gpgpu_cflog_interval != 0) {
spill_log_to_file (stdout, 1, gpu_sim_cycle);
insn_warp_occ_print(stdout);
diff --git a/src/gpgpu-sim/l2cache.cc b/src/gpgpu-sim/l2cache.cc
index 0a3d56f..6623d43 100644
--- a/src/gpgpu-sim/l2cache.cc
+++ b/src/gpgpu-sim/l2cache.cc
@@ -171,6 +171,7 @@ void memory_partition_unit::cache_cycle( unsigned cycle )
assert(!read_sent);
// L2 cache lock-up: will try again next cycle
}
+ m_stats->memlatstat_L2cache_access(mf, status);
}
} else {
// L2 is disabled or non-texture access to texture-only L2
@@ -218,26 +219,68 @@ void memory_partition_unit::print( FILE *fp ) const
m_dram->print(fp);
}
-void memory_stats_t::print( FILE *fp )
+void memory_stats_t::print_L2cache_stats( FILE *fp )
{
- fprintf(fp,"gpgpu_l2_write_miss = %d\n", L2_write_miss);
- fprintf(fp,"gpgpu_l2_write_access = %d\n", L2_write_access);
- fprintf(fp,"gpgpu_l2_read_miss = %d\n", L2_read_miss);
- fprintf(fp,"gpgpu_l2_read_access = %d\n", L2_read_access);
+ // fprintf(fp,"gpgpu_l2_write_miss = %d\n", L2_write_miss);
+ // fprintf(fp,"gpgpu_l2_write_access = %d\n", L2_write_access);
+ // fprintf(fp,"gpgpu_l2_read_miss = %d\n", L2_read_miss);
+ // fprintf(fp,"gpgpu_l2_read_access = %d\n", L2_read_access);
+ unsigned total_L2_accesses = 0;
+ unsigned total_L2_misses = 0;
+
+ for (int type = 0; type < NUM_MEM_ACCESS_TYPE; type++) {
+ for (int status = 0; status < NUM_CACHE_REQUEST_STATUS; status++) {
+ if (m_L2CacheAccessBreakdown[type][status] > 0) {
+ fprintf(fp, "L2CacheAccessBreakdown[%s][%s] = %u\n",
+ mem_access_type_str((enum mem_access_type)type),
+ cache_request_status_str((enum cache_request_status)status),
+ m_L2CacheAccessBreakdown[type][status]);
+ switch (status) {
+ case HIT:
+ case HIT_RESERVED:
+ total_L2_accesses += m_L2CacheAccessBreakdown[type][status];
+ break;
+ case MISS:
+ total_L2_accesses += m_L2CacheAccessBreakdown[type][status];
+ total_L2_misses += m_L2CacheAccessBreakdown[type][status];
+ break;
+ case RESERVATION_FAIL: break;
+ default: assert(0);
+ }
+ }
+ }
+ }
+
+ fprintf(fp, "L2Cache_Total_Accesses = %u\n", total_L2_accesses);
+ fprintf(fp, "L2Cache_Total_Misses = %u\n", total_L2_misses);
}
void memory_stats_t::visualizer_print( gzFile visualizer_file )
{
- gzprintf(visualizer_file, "Ltwowritemiss: %d\n", L2_write_miss);
- gzprintf(visualizer_file, "Ltwowritehit: %d\n", L2_write_access-L2_write_miss);
- gzprintf(visualizer_file, "Ltworeadmiss: %d\n", L2_read_miss);
- gzprintf(visualizer_file, "Ltworeadhit: %d\n", L2_read_access-L2_read_miss);
+ // gzprintf(visualizer_file, "Ltwowritemiss: %d\n", L2_write_miss);
+ // gzprintf(visualizer_file, "Ltwowritehit: %d\n", L2_write_access-L2_write_miss);
+ // gzprintf(visualizer_file, "Ltworeadmiss: %d\n", L2_read_miss);
+ // gzprintf(visualizer_file, "Ltworeadhit: %d\n", L2_read_access-L2_read_miss);
if (num_mfs)
gzprintf(visualizer_file, "averagemflatency: %lld\n", mf_total_lat/num_mfs);
}
+// record the outcome of L2 cache access by this memory request
+void memory_stats_t::memlatstat_L2cache_access(mem_fetch *mf, int access_outcome)
+{
+ switch(access_outcome) {
+ case HIT:
+ case HIT_RESERVED:
+ case MISS:
+ case RESERVATION_FAIL:
+ m_L2CacheAccessBreakdown[mf->get_access_type()][access_outcome] += 1;
+ break;
+ default: assert(0 && "Unknown cache access outcome"); break;
+ }
+}
+
void gpgpu_sim::print_dram_L2_stats(FILE *fout) const
{
diff --git a/src/gpgpu-sim/mem_latency_stat.cc b/src/gpgpu-sim/mem_latency_stat.cc
index 7324033..a2c4177 100644
--- a/src/gpgpu-sim/mem_latency_stat.cc
+++ b/src/gpgpu-sim/mem_latency_stat.cc
@@ -30,6 +30,7 @@
#include "mem_latency_stat.h"
#include "gpu-sim.h"
#include "gpu-misc.h"
+#include "gpu-cache.h"
#include "shader.h"
#include "mem_fetch.h"
#include "stat-tool.h"
@@ -124,10 +125,10 @@ memory_stats_t::memory_stats_t( unsigned n_shader, const struct shader_core_conf
}
}
- L2_write_miss=0;
- L2_write_access=0;
- L2_read_access=0;
- L2_read_miss=0;
+ // L2_write_miss=0;
+ // L2_write_access=0;
+ // L2_read_access=0;
+ // L2_read_miss=0;
L2_cbtoL2length = (unsigned int*) calloc(mem_config->m_n_mem, sizeof(unsigned int));
L2_cbtoL2writelength = (unsigned int*) calloc(mem_config->m_n_mem, sizeof(unsigned int));
L2_L2tocblength = (unsigned int*) calloc(mem_config->m_n_mem, sizeof(unsigned int));
diff --git a/src/gpgpu-sim/mem_latency_stat.h b/src/gpgpu-sim/mem_latency_stat.h
index 83114fa..4bfb165 100644
--- a/src/gpgpu-sim/mem_latency_stat.h
+++ b/src/gpgpu-sim/mem_latency_stat.h
@@ -30,6 +30,7 @@
#include <stdio.h>
#include <zlib.h>
+#include <map>
class memory_stats_t {
public:
@@ -39,12 +40,13 @@ public:
unsigned memlatstat_done( class mem_fetch *mf );
void memlatstat_read_done( class mem_fetch *mf );
+ void memlatstat_L2cache_access( class mem_fetch *mf, int access_outcome );
void memlatstat_dram_access( class mem_fetch *mf );
void memlatstat_icnt2mem_pop( class mem_fetch *mf);
void memlatstat_lat_pw();
void memlatstat_print(unsigned n_mem, unsigned gpu_mem_n_bk);
- void print( FILE *fp );
+ void print_L2cache_stats( FILE *fp );
void visualizer_print( gzFile visualizer_file );
unsigned m_n_shader;
@@ -81,11 +83,13 @@ public:
unsigned ***mem_access_type_stats; // dram access type classification
- // stats
- unsigned L2_write_access;
- unsigned L2_write_miss;
- unsigned L2_read_access;
- unsigned L2_read_miss;
+ // L2 cache stats
+ typedef std::map<int, std::map<int, unsigned> > L2CacheAccessBreakdown_t; // <access type, outcome, count>
+ L2CacheAccessBreakdown_t m_L2CacheAccessBreakdown;
+ // unsigned L2_write_access;
+ // unsigned L2_write_miss;
+ // unsigned L2_read_access;
+ // unsigned L2_read_miss;
unsigned int *L2_cbtoL2length;
unsigned int *L2_cbtoL2writelength;
unsigned int *L2_L2tocblength;
@@ -93,6 +97,7 @@ public:
unsigned int *L2_dramtoL2writelength;
unsigned int *L2_L2todramlength;
+ // DRAM access row locality stats
unsigned int **concurrent_row_access; //concurrent_row_access[dram chip id][bank id]
unsigned int **num_activates; //num_activates[dram chip id][bank id]
unsigned int **row_access; //row_access[dram chip id][bank id]
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 02:55:20 +0000