summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/gpgpu-sim/gpu-cache.h4
-rw-r--r--src/gpgpu-sim/gpu-sim.h16
-rw-r--r--src/gpgpu-sim/mem_latency_stat.h4
-rw-r--r--src/gpgpu-sim/shader.cc2
-rw-r--r--src/gpuwattch/XML_Parse.cc29
-rw-r--r--src/gpuwattch/array.cc41
-rw-r--r--src/gpuwattch/core.cc305
-rw-r--r--src/gpuwattch/iocontrollers.cc10
-rw-r--r--src/gpuwattch/logic.cc54
-rw-r--r--src/gpuwattch/logic.h8
-rw-r--r--src/gpuwattch/memoryctrl.cc35
-rw-r--r--src/gpuwattch/noc.cc46
-rw-r--r--src/gpuwattch/processor.cc5
-rw-r--r--src/gpuwattch/processor.h2
-rw-r--r--src/gpuwattch/sharedcache.cc63
-rw-r--r--src/gpuwattch/technology_xeon_core.cc4
-rw-r--r--src/gpuwattch/xmlParser.cc6
-rw-r--r--src/gpuwattch/xmlParser.h222
18 files changed, 384 insertions, 472 deletions
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index 9fe14ca..9b9898e 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -1312,9 +1312,9 @@ class baseline_cache : public cache_t {
const cache_config &m_config;
int m_data_port_occupied_cycles; //< Number of cycle that the data port
- // remains used
+ //remains used
int m_fill_port_occupied_cycles; //< Number of cycle that the fill port
- // remains used
+ //remains used
};
bandwidth_management m_bandwidth_management;
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h
index a24ceea..40c4482 100644
--- a/src/gpgpu-sim/gpu-sim.h
+++ b/src/gpgpu-sim/gpu-sim.h
@@ -264,11 +264,11 @@ class memory_config {
// GDDR5 this is identical to RTPS, if for other DRAM this is
// different, you will need to split them in two
- unsigned tCCD; // column to column delay
- unsigned tRRD; // minimal time required between activation of rows in
- // different banks
- unsigned tRCD; // row to column delay - time required to activate a row
- // before a read
+ unsigned tCCD; // column to column delay
+ unsigned tRRD; // minimal time required between activation of rows in
+ // different banks
+ unsigned tRCD; // row to column delay - time required to activate a row
+ // before a read
unsigned tRCDWR; // row to column delay for a write command
unsigned tRAS; // time needed to activate row
unsigned tRP; // row precharge ie. deactivate row
@@ -276,7 +276,7 @@ class memory_config {
tRC; // row cycle time ie. precharge current, then activate different row
unsigned tCDLR; // Last data-in to Read command (switching from write to
// read)
- unsigned tWR; // Last data-in to Row precharge
+ unsigned tWR; // Last data-in to Row precharge
unsigned CL; // CAS latency
unsigned WL; // WRITE latency
@@ -628,9 +628,9 @@ class gpgpu_sim : public gpgpu_t {
std::map<unsigned, watchpoint_event> g_watchpoint_hits;
std::string executed_kernel_info_string(); //< format the kernel information
- // into a string for stat printout
+ //into a string for stat printout
void clear_executed_kernel_info(); //< clear the kernel information after
- // stat printout
+ //stat printout
public:
unsigned long long gpu_sim_insn;
diff --git a/src/gpgpu-sim/mem_latency_stat.h b/src/gpgpu-sim/mem_latency_stat.h
index d733218..21c15ee 100644
--- a/src/gpgpu-sim/mem_latency_stat.h
+++ b/src/gpgpu-sim/mem_latency_stat.h
@@ -90,8 +90,8 @@ class memory_stats_t {
unsigned int **totalbankreads; // bankreads[dram chip id][bank id]
unsigned int **totalbankaccesses; // bankaccesses[dram chip id][bank id]
unsigned int *num_MCBs_accessed; // tracks how many memory controllers are
- // accessed whenever any thread in a warp
- // misses in cache
+ // accessed whenever any thread in a warp
+ // misses in cache
unsigned int *position_of_mrq_chosen; // position of mrq in m_queue chosen
unsigned ***mem_access_type_stats; // dram access type classification
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index fc1c1e2..73ea8b3 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -3460,7 +3460,7 @@ void shader_core_ctx::warp_exit(unsigned warp_id) {
for (unsigned i = warp_id * get_config()->warp_size;
i < (warp_id + 1) * get_config()->warp_size; i++) {
// if(this->m_thread[i]->m_functional_model_thread_state &&
- // this->m_thread[i].m_functional_model_thread_state->donecycle()==0) {
+ //this->m_thread[i].m_functional_model_thread_state->donecycle()==0) {
// done = false;
// }
diff --git a/src/gpuwattch/XML_Parse.cc b/src/gpuwattch/XML_Parse.cc
index 19d3d44..26115d3 100644
--- a/src/gpuwattch/XML_Parse.cc
+++ b/src/gpuwattch/XML_Parse.cc
@@ -535,7 +535,7 @@ void ParseXML::parse(char* filepath) {
// if (sys.Private_L2 && sys.number_of_cores!=sys.number_of_L2s)
// {
// cout<<"Private L2: Number of L2s must equal to Number of
- // Cores"<<endl;
+ //Cores"<<endl;
// exit(0);
// }
@@ -563,7 +563,7 @@ void ParseXML::parse(char* filepath) {
unsigned int OrderofComponents_3layer = 0;
if (NumofCom_3 > OrderofComponents_3layer) {
//___________________________get all
- // system.core0-n________________________________________________
+ //system.core0-n________________________________________________
if (sys.homogeneous_cores == 1)
OrderofComponents_3layer = 0;
else
@@ -2044,8 +2044,9 @@ void ParseXML::parse(char* filepath) {
if (strcmp(xNode4.getAttribute("name"), "sharedmemory") ==
0) { // find system.core0.sharedmemory
itmp = xNode4.nChildNode("param");
- for (k = 0; k < itmp; k++) { // get all items of param in
- // system.core0.sharedmemory--sharedmemory
+ for (k = 0; k < itmp;
+ k++) { // get all items of param in
+ // system.core0.sharedmemory--sharedmemory
if (strcmp(xNode4.getChildNode("param", k).getAttribute("name"),
"sharedmemory_config") == 0) {
strtmp.assign(
@@ -2482,7 +2483,7 @@ void ParseXML::parse(char* filepath) {
}
//__________________________________________Get
- // system.L1Directory0-n____________________________________________
+ //system.L1Directory0-n____________________________________________
int w, tmpOrderofComponents_3layer;
w = OrderofComponents_3layer + 1;
tmpOrderofComponents_3layer = OrderofComponents_3layer;
@@ -2648,7 +2649,7 @@ void ParseXML::parse(char* filepath) {
}
//__________________________________________Get
- // system.L2Directory0-n____________________________________________
+ //system.L2Directory0-n____________________________________________
w = OrderofComponents_3layer + 1;
tmpOrderofComponents_3layer = OrderofComponents_3layer;
if (sys.homogeneous_L2Directories == 1)
@@ -2813,7 +2814,7 @@ void ParseXML::parse(char* filepath) {
}
//__________________________________________Get
- // system.L2[0..n]____________________________________________
+ //system.L2[0..n]____________________________________________
w = OrderofComponents_3layer + 1;
tmpOrderofComponents_3layer = OrderofComponents_3layer;
if (sys.homogeneous_L2s == 1)
@@ -3101,7 +3102,7 @@ void ParseXML::parse(char* filepath) {
}
}
//__________________________________________Get
- // system.L3[0..n]____________________________________________
+ //system.L3[0..n]____________________________________________
w = OrderofComponents_3layer + 1;
tmpOrderofComponents_3layer = OrderofComponents_3layer;
if (sys.homogeneous_L3s == 1)
@@ -3389,7 +3390,7 @@ void ParseXML::parse(char* filepath) {
}
}
//__________________________________________Get
- // system.NoC[0..n]____________________________________________
+ //system.NoC[0..n]____________________________________________
w = OrderofComponents_3layer + 1;
tmpOrderofComponents_3layer = OrderofComponents_3layer;
if (sys.homogeneous_NoCs == 1)
@@ -3640,7 +3641,7 @@ void ParseXML::parse(char* filepath) {
}
}
//__________________________________________Get
- // system.mem____________________________________________
+ //system.mem____________________________________________
if (OrderofComponents_3layer > 0)
OrderofComponents_3layer = OrderofComponents_3layer + 1;
xNode3 = xNode2.getChildNode("component", OrderofComponents_3layer);
@@ -3756,7 +3757,7 @@ void ParseXML::parse(char* filepath) {
exit(0);
}
//__________________________________________Get
- // system.mc____________________________________________
+ //system.mc____________________________________________
if (OrderofComponents_3layer > 0)
OrderofComponents_3layer = OrderofComponents_3layer + 1;
xNode3 = xNode2.getChildNode("component", OrderofComponents_3layer);
@@ -3946,7 +3947,7 @@ void ParseXML::parse(char* filepath) {
exit(0);
}
//__________________________________________Get
- // system.niu____________________________________________
+ //system.niu____________________________________________
if (OrderofComponents_3layer > 0)
OrderofComponents_3layer = OrderofComponents_3layer + 1;
xNode3 = xNode2.getChildNode("component", OrderofComponents_3layer);
@@ -4004,7 +4005,7 @@ void ParseXML::parse(char* filepath) {
}
//__________________________________________Get
- // system.pcie____________________________________________
+ //system.pcie____________________________________________
if (OrderofComponents_3layer > 0)
OrderofComponents_3layer = OrderofComponents_3layer + 1;
xNode3 = xNode2.getChildNode("component", OrderofComponents_3layer);
@@ -4073,7 +4074,7 @@ void ParseXML::parse(char* filepath) {
exit(0);
}
//__________________________________________Get
- // system.flashcontroller____________________________________________
+ //system.flashcontroller____________________________________________
if (OrderofComponents_3layer > 0)
OrderofComponents_3layer = OrderofComponents_3layer + 1;
xNode3 = xNode2.getChildNode("component", OrderofComponents_3layer);
diff --git a/src/gpuwattch/array.cc b/src/gpuwattch/array.cc
index a50cac6..aca5a8a 100644
--- a/src/gpuwattch/array.cc
+++ b/src/gpuwattch/array.cc
@@ -118,7 +118,7 @@ void ArrayST::optimize_array() {
10; // This is the time_dev to be used for next iteration
// from best area to worst area -->worst timing to best
- // timing
+ //timing
if ((((local_result.cycle_time - throughput) <= 1e-10) &&
(local_result.access_time - latency) <= 1e-10) ||
(local_result.data_array2->area_efficiency <
@@ -145,8 +145,8 @@ void ArrayST::optimize_array() {
if (l_ip.cycle_time_dev > 10) { // if not >10 local_result is the last
// result, it cannot be cleaned up
- temp_res = &local_result; // Only solutions not saved in the list
- // need to be cleaned up
+ temp_res = &local_result; // Only solutions not saved in the list
+ // need to be cleaned up
temp_res->cleanup();
}
}
@@ -171,36 +171,23 @@ void ArrayST::optimize_array() {
// /*According to "Content-Addressable Memory (CAM) Circuits and
// Architectures": A Tutorial and Survey
// by Kostas Pagiamtzis et al.
- // CAM structures can be heavily pipelined and use
- // look-ahead
- // techniques,
- // therefore timing can be relaxed. But McPAT does not
- //model
- // the
- // advanced
- // techniques. If continue optimizing, the area efficiency
- //will
- // be
- // too low
+ // CAM structures can be heavily pipelined and use look-ahead
+ //techniques,
+ // therefore timing can be relaxed. But McPAT does not model the
+ //advanced
+ // techniques. If continue optimizing, the area efficiency will be
+ //too low
// */
// //For CAM and FA, stop opt if area efficiency is too low
// if (throughput_overflow==true)
- // cout<< "Warning: " <<" McPAT stopped optimization on
- //throughput
- // for
+ // cout<< "Warning: " <<" McPAT stopped optimization on throughput for
//"<< name
- // <<" array structure because its area efficiency
- //is
- // below
+ // <<" array structure because its area efficiency is below
//"<<area_efficiency_threshold<<"% " << endl;
// if (latency_overflow==true)
- // cout<< "Warning: " <<" McPAT stopped optimization on latency
- //for
- //"<<
- // name
- // <<" array structure because its area efficiency
- //is
- // below
+ // cout<< "Warning: " <<" McPAT stopped optimization on latency for "<<
+ //name
+ // <<" array structure because its area efficiency is below
//"<<area_efficiency_threshold<<"% " << endl;
// }
diff --git a/src/gpuwattch/core.cc b/src/gpuwattch/core.cc
index 6b9f0d5..9e9f1ab 100644
--- a/src/gpuwattch/core.cc
+++ b/src/gpuwattch/core.cc
@@ -59,31 +59,31 @@
//-gpgpu_num_reg_banks 8 # Number of register banks (default
//= 8)
//-gpgpu_reg_bank_use_warp_id 0 # Use warp ID in mapping
-// registers to banks (default = off)
+//registers to banks (default = off)
//-gpgpu_operand_collector_num_units_sp 6 # number of
-// collector units (default = 4)
+//collector units (default = 4)
//-gpgpu_operand_collector_num_units_sfu 8 # number of
-// collector units (default = 4)
+//collector units (default = 4)
//-gpgpu_operand_collector_num_units_mem 2 # number of
-// collector units (default = 2)
+//collector units (default = 2)
//-gpgpu_operand_collector_num_units_gen 0 # number of
-// collector units (default = 0)
+//collector units (default = 0)
//-gpgpu_operand_collector_num_in_ports_sp 1 # number of
-// collector unit in ports (default = 1)
+//collector unit in ports (default = 1)
//-gpgpu_operand_collector_num_in_ports_sfu 1 # number of
-// collector unit in ports (default = 1)
+//collector unit in ports (default = 1)
//-gpgpu_operand_collector_num_in_ports_mem 1 # number of
-// collector unit in ports (default = 1)
+//collector unit in ports (default = 1)
//-gpgpu_operand_collector_num_in_ports_gen 0 # number of
-// collector unit in ports (default = 0)
+//collector unit in ports (default = 0)
//-gpgpu_operand_collector_num_out_ports_sp 1 # number of
-// collector unit in ports (default = 1)
+//collector unit in ports (default = 1)
//-gpgpu_operand_collector_num_out_ports_sfu 1 # number of
-// collector unit in ports (default = 1)
+//collector unit in ports (default = 1)
//-gpgpu_operand_collector_num_out_ports_mem 1 # number of
-// collector unit in ports (default = 1)
+//collector unit in ports (default = 1)
//-gpgpu_operand_collector_num_out_ports_gen 0 # number of
-// collector unit in ports (default = 0)
+//collector unit in ports (default = 0)
// The total number of collector units and their input ports, and the number of
// register file banks
@@ -827,22 +827,18 @@ SchedulerU::SchedulerU(ParseXML* XML_interface, int ithCore_,
// PC is to id the instruction for recover exception.
// inst is used to map the renamed dest. registers.so that commit stage
// can know which reg/RRAT to update
- // data =
- // int(ceil((robExtra+coredynp.pc_width
+ // data = int(ceil((robExtra+coredynp.pc_width
//+
- // coredynp.instruction_length
- //+
- // 2*coredynp.phy_ireg_width)/8.0));
+ // coredynp.instruction_length +
+ //2*coredynp.phy_ireg_width)/8.0));
data = int(ceil(
(robExtra + coredynp.pc_width + coredynp.phy_ireg_width) / 8.0));
} else {
// in RS based OOO, ROB also contains value of destination reg
- // data =
- // int(ceil((robExtra+coredynp.pc_width
- //+
- // coredynp.instruction_length
+ // data = int(ceil((robExtra+coredynp.pc_width
//+
- // 2*coredynp.phy_ireg_width + coredynp.fp_data_width)/8.0));
+ // coredynp.instruction_length +
+ //2*coredynp.phy_ireg_width + coredynp.fp_data_width)/8.0));
data = int(ceil((robExtra + coredynp.pc_width +
coredynp.phy_ireg_width + coredynp.fp_data_width) /
8.0));
@@ -2403,9 +2399,8 @@ RENAMINGU::RENAMINGU(ParseXML* XML_interface, int ithCore_,
// detailed explaintions
data =
33; // int(ceil(coredynp.phy_ireg_width*(1+coredynp.globalCheckpoint)/8.0));
- // data
- //=
- // int(ceil(coredynp.phy_ireg_width/8.0));
+ // data =
+ //int(ceil(coredynp.phy_ireg_width/8.0));
out_w = 1; // int(ceil(coredynp.phy_ireg_width/8.0));
interface_ip.is_cache = false;
interface_ip.pure_cam = false;
@@ -2435,44 +2430,42 @@ RENAMINGU::RENAMINGU(ParseXML* XML_interface, int ithCore_,
XML->sys.core[ithCore].number_hardware_threads);
area.set_area(area.get_area() + iFRAT->area.get_area());
- // //RAHT According to Intel, combine GC with FRAT
- // is
- // very costly.
- // data
- //=
- // int(ceil(coredynp.phy_ireg_width/8.0)*coredynp.num_IRF_entry);
+ // //RAHT According to Intel, combine GC with FRAT is
+ //very costly.
+ // data =
+ //int(ceil(coredynp.phy_ireg_width/8.0)*coredynp.num_IRF_entry);
// out_w = data;
// interface_ip.is_cache =
- // false;
+ //false;
// interface_ip.pure_cam = false;
// interface_ip.pure_ram = true;
// interface_ip.line_sz = data;
// interface_ip.cache_sz =
- // data*coredynp.globalCheckpoint;
+ //data*coredynp.globalCheckpoint;
// interface_ip.assoc = 1;
// interface_ip.nbanks = 1;
// interface_ip.out_w = out_w*8;
// interface_ip.access_mode = 0;
// interface_ip.throughput =
- // 1.0/clockRate;
+ //1.0/clockRate;
// interface_ip.latency =
- // 1.0/clockRate;
+ //1.0/clockRate;
// interface_ip.obj_func_dyn_energy = 0;
// interface_ip.obj_func_dyn_power = 0;
// interface_ip.obj_func_leak_power = 0;
// interface_ip.obj_func_cycle_t = 1;
// interface_ip.num_rw_ports = 1;//the extra one
- // port is for GCs
+ //port is for GCs
// interface_ip.num_rd_ports =
- // 2*coredynp.decodeW;
+ //2*coredynp.decodeW;
// interface_ip.num_wr_ports = coredynp.decodeW;
// interface_ip.num_se_rd_ports = 0;
// iFRAT = new ArrayST(&interface_ip, "Int
- // FrontRAT");
+ //FrontRAT");
// iFRAT->area.set_area(iFRAT->area.get_area()+
- // iFRAT->local_result.area*XML->sys.core[ithCore].number_hardware_threads);
+ //iFRAT->local_result.area*XML->sys.core[ithCore].number_hardware_threads);
// area.set_area(area.get_area()+
- // iFRAT->area.get_area());
+ //iFRAT->area.get_area());
// FRAT floating point
data = int(ceil(coredynp.phy_freg_width *
@@ -3230,39 +3223,30 @@ void BranchPredictor::displayEnergy(uint32_t indent, int plevel, bool is_tdp) {
<< " W" << endl;
cout << endl;
} else {
- // cout << indent_str_next << "Global Predictor Peak Dynamic = "
- //<<
- // globalBPT->rt_power.readOp.dynamic*clockRate << " W" << endl;
- // cout << indent_str_next << "Global Predictor Subthreshold
- //Leakage
- //=
+ // cout << indent_str_next << "Global Predictor Peak Dynamic = " <<
+ //globalBPT->rt_power.readOp.dynamic*clockRate << " W" << endl;
+ // cout << indent_str_next << "Global Predictor Subthreshold Leakage =
//" << globalBPT->rt_power.readOp.leakage <<" W" << endl;
- // cout << indent_str_next << "Global Predictor Gate Leakage = "
- //<<
- // globalBPT->rt_power.readOp.gate_leakage << " W" << endl;
- // cout << indent_str_next << "Local Predictor Peak Dynamic = "
- //<<
- // L1_localBPT->rt_power.readOp.dynamic*clockRate << " W" << endl;
- // cout << indent_str_next << "Local Predictor Subthreshold Leakage
- //=
- //"
+ // cout << indent_str_next << "Global Predictor Gate Leakage = " <<
+ //globalBPT->rt_power.readOp.gate_leakage << " W" << endl;
+ // cout << indent_str_next << "Local Predictor Peak Dynamic = " <<
+ //L1_localBPT->rt_power.readOp.dynamic*clockRate << " W" << endl;
+ // cout << indent_str_next << "Local Predictor Subthreshold Leakage = "
//<< L1_localBPT->rt_power.readOp.leakage << " W" << endl;
- // cout << indent_str_next << "Local Predictor Gate Leakage = "
- //<<
- // L1_localBPT->rt_power.readOp.gate_leakage << " W" << endl;
+ // cout << indent_str_next << "Local Predictor Gate Leakage = " <<
+ //L1_localBPT->rt_power.readOp.gate_leakage << " W" << endl;
// cout << indent_str_next << "Chooser Peak Dynamic = " <<
- // chooser->rt_power.readOp.dynamic*clockRate << " W" << endl;
- // cout << indent_str_next << "Chooser Subthreshold Leakage = "
- //<<
- // chooser->rt_power.readOp.leakage << " W" << endl;
+ //chooser->rt_power.readOp.dynamic*clockRate << " W" << endl;
+ // cout << indent_str_next << "Chooser Subthreshold Leakage = " <<
+ //chooser->rt_power.readOp.leakage << " W" << endl;
// cout << indent_str_next << "Chooser Gate Leakage = " <<
- // chooser->rt_power.readOp.gate_leakage << " W" << endl;
+ //chooser->rt_power.readOp.gate_leakage << " W" << endl;
// cout << indent_str_next << "RAS Peak Dynamic = " <<
- // RAS->rt_power.readOp.dynamic*clockRate << " W" << endl;
+ //RAS->rt_power.readOp.dynamic*clockRate << " W" << endl;
// cout << indent_str_next << "RAS Subthreshold Leakage = " <<
- // RAS->rt_power.readOp.leakage << " W" << endl;
+ //RAS->rt_power.readOp.leakage << " W" << endl;
// cout << indent_str_next << "RAS Gate Leakage = " <<
- // RAS->rt_power.readOp.gate_leakage << " W" << endl;
+ //RAS->rt_power.readOp.gate_leakage << " W" << endl;
}
}
@@ -3609,48 +3593,30 @@ void InstFetchU::displayEnergy(uint32_t indent, int plevel, bool is_tdp) {
<< " W" << endl;
cout << endl;
} else {
- // cout << indent_str_next << "Instruction Cache Peak Dynamic =
- //"
- //<<
- // icache.rt_power.readOp.dynamic*clockRate << " W" << endl;
- // cout << indent_str_next << "Instruction Cache Subthreshold
- // Leakage
+ // cout << indent_str_next << "Instruction Cache Peak Dynamic = " <<
+ //icache.rt_power.readOp.dynamic*clockRate << " W" << endl;
+ // cout << indent_str_next << "Instruction Cache Subthreshold Leakage
//= " << icache.rt_power.readOp.leakage <<" W" << endl;
- // cout << indent_str_next << "Instruction Cache Gate Leakage =
- //"
- //<<
- // icache.rt_power.readOp.gate_leakage << " W" << endl;
- // cout << indent_str_next << "Instruction Buffer Peak Dynamic =
- //"
- //<<
- // IB->rt_power.readOp.dynamic*clockRate << " W" << endl;
- // cout << indent_str_next << "Instruction Buffer Subthreshold
- // Leakage
+ // cout << indent_str_next << "Instruction Cache Gate Leakage = " <<
+ //icache.rt_power.readOp.gate_leakage << " W" << endl;
+ // cout << indent_str_next << "Instruction Buffer Peak Dynamic = " <<
+ //IB->rt_power.readOp.dynamic*clockRate << " W" << endl;
+ // cout << indent_str_next << "Instruction Buffer Subthreshold Leakage
//= " << IB->rt_power.readOp.leakage << " W" << endl;
- // cout << indent_str_next << "Instruction Buffer Gate Leakage =
- //"
- //<<
- // IB->rt_power.readOp.gate_leakage << " W" << endl;
- // cout << indent_str_next << "Branch Target Buffer Peak Dynamic =
- //"
- //<<
- // BTB->rt_power.readOp.dynamic*clockRate << " W" << endl;
+ // cout << indent_str_next << "Instruction Buffer Gate Leakage = " <<
+ //IB->rt_power.readOp.gate_leakage << " W" << endl;
+ // cout << indent_str_next << "Branch Target Buffer Peak Dynamic = " <<
+ //BTB->rt_power.readOp.dynamic*clockRate << " W" << endl;
// cout << indent_str_next << "Branch Target Buffer Subthreshold
- // Leakage = " << BTB->rt_power.readOp.leakage << " W" << endl;
- // cout << indent_str_next << "Branch Target Buffer Gate Leakage =
- //"
- //<<
- // BTB->rt_power.readOp.gate_leakage << " W" << endl;
- // cout << indent_str_next << "Branch Predictor Peak Dynamic = "
- //<<
- // BPT->rt_power.readOp.dynamic*clockRate << " W" << endl;
- // cout << indent_str_next << "Branch Predictor Subthreshold
- //Leakage
- //=
+ //Leakage = " << BTB->rt_power.readOp.leakage << " W" << endl;
+ // cout << indent_str_next << "Branch Target Buffer Gate Leakage = " <<
+ //BTB->rt_power.readOp.gate_leakage << " W" << endl;
+ // cout << indent_str_next << "Branch Predictor Peak Dynamic = " <<
+ //BPT->rt_power.readOp.dynamic*clockRate << " W" << endl;
+ // cout << indent_str_next << "Branch Predictor Subthreshold Leakage =
//" << BPT->rt_power.readOp.leakage << " W" << endl;
- // cout << indent_str_next << "Branch Predictor Gate Leakage = "
- //<<
- // BPT->rt_power.readOp.gate_leakage << " W" << endl;
+ // cout << indent_str_next << "Branch Predictor Gate Leakage = " <<
+ //BPT->rt_power.readOp.gate_leakage << " W" << endl;
}
}
@@ -4248,12 +4214,11 @@ void SchedulerU::computeEnergy(bool is_tdp) {
if (!exist) return;
double ROB_duty_cycle;
// ROB_duty_cycle = ((coredynp.ALU_duty_cycle +
- // coredynp.num_muls>0?coredynp.MUL_duty_cycle:0
- // + coredynp.num_fpus>0?coredynp.FPU_duty_cycle:0))*1.1<1
- //?
+ //coredynp.num_muls>0?coredynp.MUL_duty_cycle:0
+ // + coredynp.num_fpus>0?coredynp.FPU_duty_cycle:0))*1.1<1 ?
//(coredynp.ALU_duty_cycle + coredynp.num_muls>0?coredynp.MUL_duty_cycle:0
// +
- // coredynp.num_fpus>0?coredynp.FPU_duty_cycle:0)*1.1:1;
+ //coredynp.num_fpus>0?coredynp.FPU_duty_cycle:0)*1.1:1;
ROB_duty_cycle = 1;
// init stats
if (is_tdp) {
@@ -4427,7 +4392,7 @@ void SchedulerU::computeEnergy(bool is_tdp) {
} else if (coredynp.multithreaded) {
// set_pppm(pppm_t,
- // XML->sys.core[ithCore].issue_width,1, 1, 1);
+ //XML->sys.core[ithCore].issue_width,1, 1, 1);
int_inst_window->power =
int_inst_window->power_t +
(int_inst_window->local_result.power + instruction_selection->power) *
@@ -4454,7 +4419,7 @@ void SchedulerU::computeEnergy(bool is_tdp) {
} else if (coredynp.multithreaded) {
// set_pppm(pppm_t,
- // XML->sys.core[ithCore].issue_width,1, 1, 1);
+ //XML->sys.core[ithCore].issue_width,1, 1, 1);
int_inst_window->rt_power =
int_inst_window->power_t +
(int_inst_window->local_result.power + instruction_selection->power) *
@@ -4464,9 +4429,9 @@ void SchedulerU::computeEnergy(bool is_tdp) {
}
// set_pppm(pppm_t, XML->sys.core[ithCore].issue_width,1, 1, 1);
// cout<<"Scheduler
- // power="<<power.readOp.dynamic<<"leakage="<<power.readOp.leakage<<endl;
+ //power="<<power.readOp.dynamic<<"leakage="<<power.readOp.leakage<<endl;
// cout<<"IW="<<int_inst_window->local_result.power.searchOp.dynamic *
- // int_inst_window->stats_t.readAc.access +
+ //int_inst_window->stats_t.readAc.access +
// + int_inst_window->local_result.power.writeOp.dynamic *
// int_inst_window->stats_t.writeAc.access<<"leakage="<<int_inst_window->local_result.power.readOp.leakage<<endl;
// cout<<"selection"<<instruction_selection->power.readOp.dynamic<<"leakage"<<instruction_selection->power.readOp.leakage<<endl;
@@ -5139,11 +5104,11 @@ void LoadStoreU::computeEnergy(bool is_tdp) {
} else {
// LSQ->power_t.readOp.dynamic +=
- // LSQ->stats_t.readAc.access*(LSQ->local_result.power.searchOp.dynamic +
- // LSQ->local_result.power.readOp.dynamic)
+ //LSQ->stats_t.readAc.access*(LSQ->local_result.power.searchOp.dynamic +
+ //LSQ->local_result.power.readOp.dynamic)
// +
- // LSQ->stats_t.writeAc.access*LSQ->local_result.power.writeOp.dynamic;//every
- // memory access invloves at least two operations on LSQ
+ //LSQ->stats_t.writeAc.access*LSQ->local_result.power.writeOp.dynamic;//every
+ //memory access invloves at least two operations on LSQ
// No LSQ in GPUs (Syed)
}
@@ -5979,7 +5944,7 @@ void EXECU::displayEnergy(uint32_t indent, int plevel, bool is_tdp) {
bool long_channel = XML->sys.longer_channel_device;
// cout << indent_str_next << "Results Broadcast Bus Area = " <<
- // bypass->area.get_area() *1e-6 << " mm^2" << endl;
+ //bypass->area.get_area() *1e-6 << " mm^2" << endl;
if (is_tdp) {
cout << indent_str << "Register Files:" << endl;
cout << indent_str_next << "Area = " << rfu->area.get_area() * 1e-6
@@ -6186,15 +6151,15 @@ void Core::computeEnergy(bool is_tdp) {
coredynp.num_pipelines / num_units,
coredynp.num_pipelines / num_units);
// cout << "IFU = " <<
- // ifu->power.readOp.dynamic*clockRate << " W" << endl;
+ //ifu->power.readOp.dynamic*clockRate << " W" << endl;
ifu->power = ifu->power + corepipe->power * pppm_t;
// cout << "IFU = " <<
- // ifu->power.readOp.dynamic*clockRate << " W" << endl;
+ //ifu->power.readOp.dynamic*clockRate << " W" << endl;
// cout << "1/4 pipe = " <<
- // corepipe->power.readOp.dynamic*clockRate/num_units << " W" << endl;
+ //corepipe->power.readOp.dynamic*clockRate/num_units << " W" << endl;
power = power + ifu->power;
// cout << "core = " <<
- // power.readOp.dynamic*clockRate << " W" << endl;
+ //power.readOp.dynamic*clockRate << " W" << endl;
}
if (lsu->exist) {
Pipeline_energy +=
@@ -6207,10 +6172,10 @@ void Core::computeEnergy(bool is_tdp) {
coredynp.num_pipelines / num_units);
lsu->power = lsu->power + corepipe->power * pppm_t;
// cout << "LSU = " <<
- // lsu->power.readOp.dynamic*clockRate << " W" << endl;
+ //lsu->power.readOp.dynamic*clockRate << " W" << endl;
power = power + lsu->power;
// cout << "core = " <<
- // power.readOp.dynamic*clockRate << " W" << endl;
+ //power.readOp.dynamic*clockRate << " W" << endl;
}
if (exu->exist) {
Pipeline_energy +=
@@ -6224,10 +6189,10 @@ void Core::computeEnergy(bool is_tdp) {
// cout<<"ExPowerScalingFactor:"<<coredynp.num_pipelines/num_units*coredynp.ALU_duty_cycle<<endl;
exu->power = exu->power + corepipe->power * pppm_t;
// cout << "EXE = " <<
- // exu->power.readOp.dynamic*clockRate << " W" << endl;
+ //exu->power.readOp.dynamic*clockRate << " W" << endl;
power = power + exu->power;
// cout << "core = " <<
- // power.readOp.dynamic*clockRate << " W" << endl;
+ //power.readOp.dynamic*clockRate << " W" << endl;
}
if (mmu->exist) {
Pipeline_energy +=
@@ -6240,10 +6205,10 @@ void Core::computeEnergy(bool is_tdp) {
coredynp.num_pipelines / num_units);
mmu->power = mmu->power + corepipe->power * pppm_t;
// cout << "MMU = " <<
- // mmu->power.readOp.dynamic*clockRate << " W" << endl;
+ //mmu->power.readOp.dynamic*clockRate << " W" << endl;
power = power + mmu->power;
// cout << "core = " <<
- // power.readOp.dynamic*clockRate << " W" << endl;
+ //power.readOp.dynamic*clockRate << " W" << endl;
}
power = power + undiffCore->power;
@@ -6311,9 +6276,8 @@ void Core::computeEnergy(bool is_tdp) {
}
rt_power = rt_power + undiffCore->power;
- // cout << "EXE = " << exu->power.readOp.dynamic*clockRate << " W"
- //<<
- // endl;
+ // cout << "EXE = " << exu->power.readOp.dynamic*clockRate << " W" <<
+ //endl;
if (XML->sys.Private_L2) {
l2cache->computeEnergy(is_tdp);
// set_pppm(pppm_t,1/l2cache->cachep.executionTime, 1,1,1);
@@ -6472,28 +6436,22 @@ void Core::displayEnergy(uint32_t indent, int plevel, bool is_tdp) {
// if (undiffCore->exist)
// {
// cout << indent_str << "Undifferentiated Core" <<
- // endl;
+ //endl;
// cout << indent_str_next << "Area = " <<
- // undiffCore->area.get_area()*1e-6<< " mm^2" << endl;
+ //undiffCore->area.get_area()*1e-6<< " mm^2" << endl;
// cout << indent_str_next << "Peak Dynamic = " <<
- // undiffCore->power.readOp.dynamic*clockRate << " W" << endl;
- //// cout << indent_str_next << "Subthreshold Leakage =
- ///"
- ///<<
- /// undiffCore->power.readOp.leakage <<" W" << endl;
- // cout << indent_str_next << "Subthreshold Leakage
- //=
+ //undiffCore->power.readOp.dynamic*clockRate << " W" << endl;
+ //// cout << indent_str_next << "Subthreshold Leakage = " <<
+ ///undiffCore->power.readOp.leakage <<" W" << endl;
+ // cout << indent_str_next << "Subthreshold Leakage =
//"
- // <<
- //(long_channel?
- // undiffCore->power.readOp.longer_channel_leakage:undiffCore->power.readOp.leakage)
+ // << (long_channel?
+ //undiffCore->power.readOp.longer_channel_leakage:undiffCore->power.readOp.leakage)
//<< " W" << endl;
// cout << indent_str_next << "Gate Leakage = " <<
- // undiffCore->power.readOp.gate_leakage << " W" << endl;
- // // cout << indent_str_next << "Runtime Dynamic =
- //"
- //<<
- // undiffCore->rt_power.readOp.dynamic/executionTime << " W" << endl;
+ //undiffCore->power.readOp.gate_leakage << " W" << endl;
+ // // cout << indent_str_next << "Runtime Dynamic = " <<
+ //undiffCore->rt_power.readOp.dynamic/executionTime << " W" << endl;
// cout <<endl;
// }
// }
@@ -6507,44 +6465,30 @@ void Core::displayEnergy(uint32_t indent, int plevel, bool is_tdp) {
<< endl;
} else {
- // cout << indent_str_next << "Instruction Fetch Unit Peak Dynamic
- //=
- //"
+ // cout << indent_str_next << "Instruction Fetch Unit Peak Dynamic = "
//<< ifu->rt_power.readOp.dynamic*clockRate << " W" << endl;
- // cout << indent_str_next << "Instruction Fetch Unit Subthreshold
- // Leakage = " << ifu->rt_power.readOp.leakage <<" W" << endl;
- // cout << indent_str_next << "Instruction Fetch Unit Gate Leakage
- //=
- //"
+ // cout << indent_str_next << "Instruction Fetch Unit Subthreshold
+ //Leakage = " << ifu->rt_power.readOp.leakage <<" W" << endl;
+ // cout << indent_str_next << "Instruction Fetch Unit Gate Leakage = "
//<< ifu->rt_power.readOp.gate_leakage << " W" << endl;
- // cout << indent_str_next << "Load Store Unit Peak Dynamic = "
- //<<
- // lsu->rt_power.readOp.dynamic*clockRate << " W" << endl;
- // cout << indent_str_next << "Load Store Unit Subthreshold Leakage
- //=
- //"
+ // cout << indent_str_next << "Load Store Unit Peak Dynamic = " <<
+ //lsu->rt_power.readOp.dynamic*clockRate << " W" << endl;
+ // cout << indent_str_next << "Load Store Unit Subthreshold Leakage = "
//<< lsu->rt_power.readOp.leakage << " W" << endl;
- // cout << indent_str_next << "Load Store Unit Gate Leakage = "
- //<<
- // lsu->rt_power.readOp.gate_leakage << " W" << endl;
- // cout << indent_str_next << "Memory Management Unit Peak Dynamic
- //=
- //"
+ // cout << indent_str_next << "Load Store Unit Gate Leakage = " <<
+ //lsu->rt_power.readOp.gate_leakage << " W" << endl;
+ // cout << indent_str_next << "Memory Management Unit Peak Dynamic = "
//<< mmu->rt_power.readOp.dynamic*clockRate << " W" << endl;
- // cout << indent_str_next << "Memory Management Unit Subthreshold
- // Leakage = " << mmu->rt_power.readOp.leakage << " W" << endl;
- // cout << indent_str_next << "Memory Management Unit Gate Leakage
- //=
- //"
+ // cout << indent_str_next << "Memory Management Unit Subthreshold
+ //Leakage = " << mmu->rt_power.readOp.leakage << " W" << endl;
+ // cout << indent_str_next << "Memory Management Unit Gate Leakage = "
//<< mmu->rt_power.readOp.gate_leakage << " W" << endl;
// cout << indent_str_next << "Execution Unit Peak Dynamic = " <<
- // exu->rt_power.readOp.dynamic*clockRate << " W" << endl;
- // cout << indent_str_next << "Execution Unit Subthreshold Leakage
- //=
- //"
+ //exu->rt_power.readOp.dynamic*clockRate << " W" << endl;
+ // cout << indent_str_next << "Execution Unit Subthreshold Leakage = "
//<< exu->rt_power.readOp.leakage << " W" << endl;
// cout << indent_str_next << "Execution Unit Gate Leakage = " <<
- // exu->rt_power.readOp.gate_leakage << " W" << endl;
+ //exu->rt_power.readOp.gate_leakage << " W" << endl;
}
}
InstFetchU::~InstFetchU() {
@@ -6867,9 +6811,8 @@ void Core::set_core_param() {
}
// if (coredynp.core_ty==OOO)
// {
- // cout<<"OOO processor models are being updated and will be
- // available
- // in next release"<<endl;
+ // cout<<"OOO processor models are being updated and will be available
+ //in next release"<<endl;
// exit(0);
// }
if (!((coredynp.scheu_ty == PhysicalRegFile) ||
diff --git a/src/gpuwattch/iocontrollers.cc b/src/gpuwattch/iocontrollers.cc
index 6a29add..2425d40 100644
--- a/src/gpuwattch/iocontrollers.cc
+++ b/src/gpuwattch/iocontrollers.cc
@@ -236,7 +236,7 @@ void NIUController::set_niu_param() {
niup.perc_load = XML->sys.niu.total_load_perc;
niup.type = XML->sys.niu.type;
// niup.executionTime =
- // XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6);
+ //XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6);
}
PCIeController::PCIeController(ParseXML* XML_interface,
@@ -276,7 +276,7 @@ PCIeController::PCIeController(ParseXML* XML_interface,
1.1 * (interface_ip.F_sz_nm / 65.0);
// //Cadence ChipEstimate using 65nm soft IP;
// frontend_dyn =
- // 0.27e-9/8*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0);
+ //0.27e-9/8*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0);
// SerDer_dyn is power not energy, scaling from 10mw/Gb/s @90nm
SerDer_dyn = 0.01 * 4 * (interface_ip.F_sz_um / 0.09) *
g_tp.peri_global.Vdd / 1.2 * g_tp.peri_global.Vdd /
@@ -305,7 +305,7 @@ PCIeController::PCIeController(ParseXML* XML_interface,
1.1 * (interface_ip.F_sz_nm / 65.0);
// //Cadence ChipEstimate using 65nm soft IP;
// frontend_dyn =
- // 0.27e-9/8*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0);
+ //0.27e-9/8*g_tp.peri_global.Vdd/1.1*g_tp.peri_global.Vdd/1.1*(interface_ip.F_sz_nm/65.0);
// SerDer_dyn is power not energy, scaling from 10mw/Gb/s @90nm
SerDer_dyn = 0.01 * 4 * (interface_ip.F_sz_um / 0.09) *
g_tp.peri_global.Vdd / 1.2 * g_tp.peri_global.Vdd /
@@ -387,7 +387,7 @@ void PCIeController::set_pcie_param() {
pciep.type = XML->sys.pcie.type;
pciep.withPHY = XML->sys.pcie.withPHY;
// pciep.executionTime =
- // XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6);
+ //XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6);
}
FlashController::FlashController(ParseXML* XML_interface,
@@ -507,5 +507,5 @@ void FlashController::set_fc_param() {
fcp.type = XML->sys.flashc.type;
fcp.withPHY = XML->sys.flashc.withPHY;
// flashcp.executionTime =
- // XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6);
+ //XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6);
}
diff --git a/src/gpuwattch/logic.cc b/src/gpuwattch/logic.cc
index d6937ca..65e3875 100644
--- a/src/gpuwattch/logic.cc
+++ b/src/gpuwattch/logic.cc
@@ -362,8 +362,8 @@ void Pipeline::compute() {
double clock_power_pipereg = num_piperegs * pipe_reg.e_clock.readOp.dynamic;
//******************pipeline power: currently, we average all the
- // possibilities of the states of DFFs in the pipeline. A better way to do it
- // is to consider
+ //possibilities of the states of DFFs in the pipeline. A better way to do it
+ //is to consider
// the harming distance of two consecutive signals, However McPAT does not
// have plan to do this in near future as it focuses on worst case power.
double pipe_reg_power = num_piperegs * (pipe_reg.e_switch.readOp.dynamic +
@@ -578,8 +578,8 @@ FunctionalUnit::FunctionalUnit(ParseXML *XML_interface, int ithCore_,
// energy = 0.3529/10*1e-9;//this is the energy(nJ) for a FP instruction
// in FPU usually it can have up to 20 cycles.
// base_energy = coredynp.core_ty==Inorder? 0:
- // 89e-3*3; //W The base energy of ALU average numbers from Intel 4G and
- // 773Mhz (Wattch)
+ //89e-3*3; //W The base energy of ALU average numbers from Intel 4G and
+ //773Mhz (Wattch)
// base_energy
//*=(g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2);
base_energy = 0;
@@ -615,8 +615,8 @@ FunctionalUnit::FunctionalUnit(ParseXML *XML_interface, int ithCore_,
g_tp.peri_global.Vdd / 2;
leakage = 0;
// base_energy = coredynp.core_ty==Inorder?
- // 0:89e-3; //W The base energy of ALU average numbers from Intel 4G and
- // 773Mhz (Wattch)
+ //0:89e-3; //W The base energy of ALU average numbers from Intel 4G and
+ //773Mhz (Wattch)
// base_energy
//*=(g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2);
base_energy = 0;
@@ -645,8 +645,8 @@ FunctionalUnit::FunctionalUnit(ParseXML *XML_interface, int ithCore_,
inv) *
g_tp.peri_global.Vdd / 2;
// base_energy = coredynp.core_ty==Inorder?
- // 0:89e-3*2; //W The base energy of ALU average numbers from Intel 4G and
- // 773Mhz (Wattch)
+ //0:89e-3*2; //W The base energy of ALU average numbers from Intel 4G and
+ //773Mhz (Wattch)
// base_energy
//*=(g_tp.peri_global.Vdd*g_tp.peri_global.Vdd/1.2/1.2);
base_energy = 0;
@@ -666,7 +666,7 @@ FunctionalUnit::FunctionalUnit(ParseXML *XML_interface, int ithCore_,
}
per_access_energy *= 0.5; // According to ARM data embedded processor has
// much lower per acc energy
- } /* if (XML->sys.Embedded) */
+ } /* if (XML->sys.Embedded) */
else {
if (fu_type == FPU) {
num_fu = coredynp.num_fpus;
@@ -705,14 +705,16 @@ FunctionalUnit::FunctionalUnit(ParseXML *XML_interface, int ithCore_,
if (g_ip->F_sz_nm > 90)
area_t = 8.47 * 1e6 *
g_tp.scaling_factor.logic_scaling_co_eff; // this is um^2
- leakage = 37e-3; // area_t
- // *(g_tp.scaling_factor.core_tx_density)*cmos_Isub_leakage(5*g_tp.min_w_nmos_,
- // 5*g_tp.min_w_nmos_*pmos_to_nmos_sizing_r, 1,
- // inv)*g_tp.peri_global.Vdd/2;//unit W
- gate_leakage = 0; // area_t
- // *(g_tp.scaling_factor.core_tx_density)*cmos_Ig_leakage(5*g_tp.min_w_nmos_,
- // 5*g_tp.min_w_nmos_*pmos_to_nmos_sizing_r, 1,
- // inv)*g_tp.peri_global.Vdd/2;//unit W
+ leakage =
+ 37e-3; // area_t
+ // *(g_tp.scaling_factor.core_tx_density)*cmos_Isub_leakage(5*g_tp.min_w_nmos_,
+ // 5*g_tp.min_w_nmos_*pmos_to_nmos_sizing_r, 1,
+ // inv)*g_tp.peri_global.Vdd/2;//unit W
+ gate_leakage =
+ 0; // area_t
+ // *(g_tp.scaling_factor.core_tx_density)*cmos_Ig_leakage(5*g_tp.min_w_nmos_,
+ // 5*g_tp.min_w_nmos_*pmos_to_nmos_sizing_r, 1,
+ // inv)*g_tp.peri_global.Vdd/2;//unit W
// energy = 0.3529/10*1e-9;//this is the energy(nJ) for a FP instruction
// in FPU usually it can have up to 20 cycles.
base_energy =
@@ -936,7 +938,7 @@ void FunctionalUnit::displayEnergy(uint32_t indent, int plevel, bool is_tdp) {
bool long_channel = XML->sys.longer_channel_device;
// cout << indent_str_next << "Results Broadcast Bus Area = " <<
- // bypass->area.get_area() *1e-6 << " mm^2" << endl;
+ //bypass->area.get_area() *1e-6 << " mm^2" << endl;
if (is_tdp) {
if (fu_type == FPU) {
cout << indent_str
@@ -1167,11 +1169,10 @@ UndiffCore::UndiffCore(ParseXML *XML_interface, int ithCore_,
// double vt=g_tp.peri_global.Vth;
// double velocity_index=1.1;
// double c_in=gate_C(g_tp.min_w_nmos_,
- // g_tp.min_w_nmos_*pmos_to_nmos_sizing_r , 0.0, false);
- // double c_out= drain_C_(g_tp.min_w_nmos_, NCH, 2, 1,
- // g_tp.cell_h_def,
- // false) + drain_C_(g_tp.min_w_nmos_*pmos_to_nmos_sizing_r, PCH, 1, 1,
- // g_tp.cell_h_def, false) + c_in;
+ //g_tp.min_w_nmos_*pmos_to_nmos_sizing_r , 0.0, false);
+ // double c_out= drain_C_(g_tp.min_w_nmos_, NCH, 2, 1, g_tp.cell_h_def,
+ //false) + drain_C_(g_tp.min_w_nmos_*pmos_to_nmos_sizing_r, PCH, 1, 1,
+ //g_tp.cell_h_def, false) + c_in;
// double w_nmos=g_tp.min_w_nmos_;
// double w_pmos=g_tp.min_w_nmos_*pmos_to_nmos_sizing_r;
// double i_on_n=1.0;
@@ -1180,16 +1181,15 @@ UndiffCore::UndiffCore(ParseXML *XML_interface, int ithCore_,
// double i_on_p_in=1;
// double vdd=g_tp.peri_global.Vdd;
- // power.readOp.sc=shortcircuit_simple(vt, velocity_index, c_in,
- // c_out,
- // w_nmos,w_pmos, i_on_n, i_on_p,i_on_n_in, i_on_p_in, vdd);
+ // power.readOp.sc=shortcircuit_simple(vt, velocity_index, c_in, c_out,
+ //w_nmos,w_pmos, i_on_n, i_on_p,i_on_n_in, i_on_p_in, vdd);
// power.readOp.dynamic=c_out*vdd*vdd/2;
// cout<<power.readOp.dynamic << "dynamic" <<endl;
// cout<<power.readOp.sc << "sc" << endl;
// power.readOp.sc=shortcircuit(vt, velocity_index, c_in, c_out,
- // w_nmos,w_pmos, i_on_n, i_on_p,i_on_n_in, i_on_p_in, vdd);
+ //w_nmos,w_pmos, i_on_n, i_on_p,i_on_n_in, i_on_p_in, vdd);
// power.readOp.dynamic=c_out*vdd*vdd/2;
//
// cout<<power.readOp.dynamic << "dynamic" <<endl;
diff --git a/src/gpuwattch/logic.h b/src/gpuwattch/logic.h
index 9a1d3e6..df00837 100644
--- a/src/gpuwattch/logic.h
+++ b/src/gpuwattch/logic.h
@@ -172,9 +172,9 @@ class Pipeline : public Component {
double WNANDp;
double load_per_pipeline_stage;
// int Hthread, num_thread, fetchWidth, decodeWidth, issueWidth,
- // commitWidth, instruction_length;
+ //commitWidth, instruction_length;
// int PC_width, opcode_length, num_arch_reg_tag,
- // data_width,num_phsical_reg_tag, address_width;
+ //data_width,num_phsical_reg_tag, address_width;
// bool thread_clock_gated;
// bool in_order, multithreaded;
void compute_stage_vector();
@@ -185,9 +185,9 @@ class Pipeline : public Component {
// class core_pipeline :public pipeline{
// public:
// int Hthread, num_thread, fetchWidth, decodeWidth, issueWidth,
-// commitWidth, instruction_length;
+//commitWidth, instruction_length;
// int PC_width, opcode_length, num_arch_reg_tag,
-// data_width,num_phsical_reg_tag, address_width;
+//data_width,num_phsical_reg_tag, address_width;
// bool thread_clock_gated;
// bool in_order, multithreaded;
// core_pipeline(bool _is_default, const InputParameter
diff --git a/src/gpuwattch/memoryctrl.cc b/src/gpuwattch/memoryctrl.cc
index d0becc4..07e2f77 100644
--- a/src/gpuwattch/memoryctrl.cc
+++ b/src/gpuwattch/memoryctrl.cc
@@ -102,7 +102,7 @@ void MCBackend::compute() {
// double max_row_addr_width = 20.0;//Current address 12~18bits
double C_MCB, mc_power, backend_dyn,
backend_gates; //, refresh_period,refresh_freq;//Equivalent per bit Cap
- // for backend,
+ //for backend,
double pmos_to_nmos_sizing_r = pmos_to_nmos_sz_ratio();
double NMOS_sizing, PMOS_sizing;
@@ -535,7 +535,7 @@ MCFrontEnd::MCFrontEnd(ParseXML* XML_interface, InputParameter* interface_ip_,
PRT->local_result.area * XML->sys.mc.memory_channels_per_mc);
//***ThreadMasks storage (coalesced threads whose memory requests are
- // satisfied by each memory access)
+ //satisfied by each memory access)
/* contents of the thread masks Array
* 16-bit bit masks for up to 16 memory requests of a warp | Number of
* pending memory requests (5 bits)
@@ -983,7 +983,7 @@ MemoryController::MemoryController(ParseXML* XML_interface,
area.set_area(area.get_area() + PHY->area.get_area());
}
//+++++++++Transaction engine +++++++++++++++++ ////TODO needs better numbers,
- // Run the RTL code from OpenSparc.
+ //Run the RTL code from OpenSparc.
// transecEngine.initialize(&interface_ip);
// transecEngine.peakDataTransferRate = XML->sys.mem.peak_transfer_rate;
// transecEngine.memDataWidth = dataBusWidth;
@@ -1023,7 +1023,7 @@ MemoryController::MemoryController(ParseXML* XML_interface,
//// //clock
//// clockNetwork.init_wire_external(is_default, &interface_ip);
//// clockNetwork.clk_area =area*1.1;//10% of placement overhead.
- /// rule of thumb
+ ///rule of thumb
//// clockNetwork.end_wiring_level =5;//toplevel metal
//// clockNetwork.start_wiring_level =5;//toplevel metal
//// clockNetwork.num_regs = pipeLogic.tot_stage_vector;
@@ -1199,7 +1199,7 @@ void MemoryController::set_mc_param() {
mcp.reads = XML->sys.mc.memory_reads;
mcp.writes = XML->sys.mc.memory_writes;
//+++++++++Transaction engine +++++++++++++++++ ////TODO needs better
- // numbers, Run the RTL code from OpenSparc.
+ //numbers, Run the RTL code from OpenSparc.
mcp.peakDataTransferRate = XML->sys.mc.peak_transfer_rate;
mcp.memRank = XML->sys.mc.number_ranks;
//++++++++++++++PHY ++++++++++++++++++++++++++ //TODO needs better numbers
@@ -1214,17 +1214,16 @@ void MemoryController::set_mc_param() {
// else if (mc_type==FLASHC)
// {
// mcp.clockRate =XML->sys.flashc.mc_clock*2;//DDR double
- // pumped
+ //pumped
// mcp.clockRate *= 1e6;
// mcp.executionTime =
- // XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6);
+ //XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6);
//
// mcp.llcBlockSize
//=int(ceil(XML->sys.flashc.llc_line_length/8.0))+XML->sys.flashc.llc_line_length;//ecc
- // overhead
- // mcp.dataBusWidth =int(ceil(XML->sys.flashc.databus_width/8.0))
- //+
- // XML->sys.flashc.databus_width;
+ //overhead
+ // mcp.dataBusWidth =int(ceil(XML->sys.flashc.databus_width/8.0)) +
+ //XML->sys.flashc.databus_width;
// mcp.addressBusWidth
//=int(ceil(XML->sys.flashc.addressbus_width));//XML->sys.physical_address_width;
// mcp.opcodeW =16;
@@ -1233,18 +1232,16 @@ void MemoryController::set_mc_param() {
// mcp.reads = XML->sys.flashc.memory_reads;
// mcp.writes = XML->sys.flashc.memory_writes;
// //+++++++++Transaction engine +++++++++++++++++ ////TODO needs
- // better numbers, Run the RTL code from OpenSparc.
+ //better numbers, Run the RTL code from OpenSparc.
// mcp.peakDataTransferRate = XML->sys.flashc.peak_transfer_rate;
// mcp.memRank = XML->sys.flashc.number_ranks;
- // //++++++++++++++PHY ++++++++++++++++++++++++++ //TODO needs
- // better
- // numbers
+ // //++++++++++++++PHY ++++++++++++++++++++++++++ //TODO needs better
+ //numbers
// //PHY.memAccesses=PHY.peakDataTransferRate;//this is the max
- // power
+ //power
// //PHY.llcBlocksize=llcBlockSize;
- // mcp.frontend_duty_cycle = 0.5;//for max power, the actual
- // off-chip
- // links is bidirectional but time shared
+ // mcp.frontend_duty_cycle = 0.5;//for max power, the actual off-chip
+ //links is bidirectional but time shared
// mcp.LVDS = XML->sys.flashc.LVDS;
// mcp.type = XML->sys.flashc.type;
// }
diff --git a/src/gpuwattch/noc.cc b/src/gpuwattch/noc.cc
index 85fc0a9..bf8d8b5 100644
--- a/src/gpuwattch/noc.cc
+++ b/src/gpuwattch/noc.cc
@@ -357,44 +357,30 @@ void NoC::displayEnergy(uint32_t indent, int plevel, bool is_tdp) {
cout << endl;
}
} else {
- // cout << indent_str_next << "Instruction Fetch Unit Peak Dynamic
- //=
- //"
+ // cout << indent_str_next << "Instruction Fetch Unit Peak Dynamic = "
//<< ifu->rt_power.readOp.dynamic*clockRate << " W" << endl;
- // cout << indent_str_next << "Instruction Fetch Unit Subthreshold
- // Leakage = " << ifu->rt_power.readOp.leakage <<" W" << endl;
- // cout << indent_str_next << "Instruction Fetch Unit Gate Leakage
- //=
- //"
+ // cout << indent_str_next << "Instruction Fetch Unit Subthreshold
+ //Leakage = " << ifu->rt_power.readOp.leakage <<" W" << endl;
+ // cout << indent_str_next << "Instruction Fetch Unit Gate Leakage = "
//<< ifu->rt_power.readOp.gate_leakage << " W" << endl;
- // cout << indent_str_next << "Load Store Unit Peak Dynamic = "
- //<<
- // lsu->rt_power.readOp.dynamic*clockRate << " W" << endl;
- // cout << indent_str_next << "Load Store Unit Subthreshold Leakage
- //=
- //"
+ // cout << indent_str_next << "Load Store Unit Peak Dynamic = " <<
+ //lsu->rt_power.readOp.dynamic*clockRate << " W" << endl;
+ // cout << indent_str_next << "Load Store Unit Subthreshold Leakage = "
//<< lsu->rt_power.readOp.leakage << " W" << endl;
- // cout << indent_str_next << "Load Store Unit Gate Leakage = "
- //<<
- // lsu->rt_power.readOp.gate_leakage << " W" << endl;
- // cout << indent_str_next << "Memory Management Unit Peak Dynamic
- //=
- //"
+ // cout << indent_str_next << "Load Store Unit Gate Leakage = " <<
+ //lsu->rt_power.readOp.gate_leakage << " W" << endl;
+ // cout << indent_str_next << "Memory Management Unit Peak Dynamic = "
//<< mmu->rt_power.readOp.dynamic*clockRate << " W" << endl;
- // cout << indent_str_next << "Memory Management Unit Subthreshold
- // Leakage = " << mmu->rt_power.readOp.leakage << " W" << endl;
- // cout << indent_str_next << "Memory Management Unit Gate Leakage
- //=
- //"
+ // cout << indent_str_next << "Memory Management Unit Subthreshold
+ //Leakage = " << mmu->rt_power.readOp.leakage << " W" << endl;
+ // cout << indent_str_next << "Memory Management Unit Gate Leakage = "
//<< mmu->rt_power.readOp.gate_leakage << " W" << endl;
// cout << indent_str_next << "Execution Unit Peak Dynamic = " <<
- // exu->rt_power.readOp.dynamic*clockRate << " W" << endl;
- // cout << indent_str_next << "Execution Unit Subthreshold Leakage
- //=
- //"
+ //exu->rt_power.readOp.dynamic*clockRate << " W" << endl;
+ // cout << indent_str_next << "Execution Unit Subthreshold Leakage = "
//<< exu->rt_power.readOp.leakage << " W" << endl;
// cout << indent_str_next << "Execution Unit Gate Leakage = " <<
- // exu->rt_power.readOp.gate_leakage << " W" << endl;
+ //exu->rt_power.readOp.gate_leakage << " W" << endl;
}
}
diff --git a/src/gpuwattch/processor.cc b/src/gpuwattch/processor.cc
index b5b5cfb..96c3351 100644
--- a/src/gpuwattch/processor.cc
+++ b/src/gpuwattch/processor.cc
@@ -1084,8 +1084,7 @@ void Processor::set_proc_param() {
// if (procdynp.numCore<1)
// {
- // cout<<" The target processor should at least have one core on
- // chip."
+ // cout<<" The target processor should at least have one core on chip."
//<<endl;
// exit(0);
// }
@@ -1136,7 +1135,7 @@ void Processor::set_proc_param() {
interface_ip.F_sz_um = interface_ip.F_sz_nm / 1000;
//***********This section of code does not have real meaning, they are just to
- // ensure all data will have initial value to prevent errors.
+ //ensure all data will have initial value to prevent errors.
// They will be overridden during each components initialization
interface_ip.cache_sz = 64;
interface_ip.line_sz = 1;
diff --git a/src/gpuwattch/processor.h b/src/gpuwattch/processor.h
index c0be8be..326206c 100644
--- a/src/gpuwattch/processor.h
+++ b/src/gpuwattch/processor.h
@@ -176,7 +176,7 @@ class Processor : public Component {
read_coef = l2array[0]
->unicache.caches->local_result.tag_array2->power.writeOp
.dynamic; //*(32/4); // removed by Jingwen, the scaling
- // of 32/4 is not used in the mcpat
+ //of 32/4 is not used in the mcpat
read_coef +=
l2array[0]->unicache.caches->local_result.power.writeOp.dynamic;
read_coef +=
diff --git a/src/gpuwattch/sharedcache.cc b/src/gpuwattch/sharedcache.cc
index d25d1df..147be43 100644
--- a/src/gpuwattch/sharedcache.cc
+++ b/src/gpuwattch/sharedcache.cc
@@ -1106,25 +1106,24 @@ void SharedCache::displayEnergy(uint32_t indent, bool is_tdp) {
// ///cout<<"directory.maxPower=" <<directory.maxPower<<endl;
//
// directory.maxPower +=
-// directory.missb.l_ip.num_search_ports*directory.missb.local_result.power.searchOp.dynamic*clockRate;
+//directory.missb.l_ip.num_search_ports*directory.missb.local_result.power.searchOp.dynamic*clockRate;
// ///cout<<"directory.maxPower=" <<directory.maxPower<<endl;
//
// directory.maxPower +=
-// directory.ifb.l_ip.num_search_ports*directory.ifb.local_result.power.searchOp.dynamic*clockRate;
+//directory.ifb.l_ip.num_search_ports*directory.ifb.local_result.power.searchOp.dynamic*clockRate;
// ///cout<<"directory.maxPower=" <<directory.maxPower<<endl;
//
// directory.maxPower +=
-// directory.prefetchb.l_ip.num_search_ports*directory.prefetchb.local_result.power.searchOp.dynamic*clockRate;
+//directory.prefetchb.l_ip.num_search_ports*directory.prefetchb.local_result.power.searchOp.dynamic*clockRate;
// ///cout<<"directory.maxPower=" <<directory.maxPower<<endl;
//
// directory.maxPower +=
-// directory.wbb.l_ip.num_search_ports*directory.wbb.local_result.power.searchOp.dynamic*clockRate;
+//directory.wbb.l_ip.num_search_ports*directory.wbb.local_result.power.searchOp.dynamic*clockRate;
//
-// cc.power.readOp.dynamic = directory.maxPower*scktRatio*8;//8
-// is
-// the memory controller counts
+// cc.power.readOp.dynamic = directory.maxPower*scktRatio*8;//8 is
+//the memory controller counts
// cc.power.readOp.leakage =
-// directory.caches.local_result.power.readOp.leakage +
+//directory.caches.local_result.power.readOp.leakage +
// directory.missb.local_result.power.readOp.leakage
// +
// directory.ifb.local_result.power.readOp.leakage
@@ -1141,23 +1140,23 @@ void SharedCache::displayEnergy(uint32_t indent, bool is_tdp) {
// ccTot.area.set_area(cc.area.get_area()*1e-6);
// ccTot.power = cc.power;
// cout<<"DC energy per access" <<
-// cc.power.readOp.dynamic/clockRate/8;
+//cc.power.readOp.dynamic/clockRate/8;
// }
// else if (XML->sys.first_level_dir==1)
// {
// inv_dir.maxPower =
-// inv_dir.caches.local_result.power.searchOp.dynamic*clockRate*XML->sys.domain_size;
+//inv_dir.caches.local_result.power.searchOp.dynamic*clockRate*XML->sys.domain_size;
// cc.power.readOp.dynamic =
-// inv_dir.maxPower*scktRatio*64/XML->sys.domain_size;
+//inv_dir.maxPower*scktRatio*64/XML->sys.domain_size;
// cc.power.readOp.leakage =
-// inv_dir.caches.local_result.power.readOp.leakage*inv_dir.caches.l_ip.nbanks*64/XML->sys.domain_size;
+//inv_dir.caches.local_result.power.readOp.leakage*inv_dir.caches.l_ip.nbanks*64/XML->sys.domain_size;
//
// cc.area.set_area(inv_dir.area*64/XML->sys.domain_size);
// cout<<"CC area="<<cc.area.get_area()*1e-6<<endl;
// cout<<"CC Power="<<cc.power.readOp.dynamic<<endl;
// ccTot.area.set_area(cc.area.get_area()*1e-6);
// cout<<"DC energy per access" <<
-// cc.power.readOp.dynamic/clockRate/8;
+//cc.power.readOp.dynamic/clockRate/8;
// ccTot.power = cc.power;
// }
// }
@@ -1174,27 +1173,27 @@ void SharedCache::displayEnergy(uint32_t indent, bool is_tdp) {
//<<directory.maxPower<<endl;
//
// directory.maxPower +=
-// directory.missb.l_ip.num_search_ports*directory.missb.local_result.power.searchOp.dynamic*clockRate;
+//directory.missb.l_ip.num_search_ports*directory.missb.local_result.power.searchOp.dynamic*clockRate;
// ///cout<<"directory.maxPower="
//<<directory.maxPower<<endl;
//
// directory.maxPower +=
-// directory.ifb.l_ip.num_search_ports*directory.ifb.local_result.power.searchOp.dynamic*clockRate;
+//directory.ifb.l_ip.num_search_ports*directory.ifb.local_result.power.searchOp.dynamic*clockRate;
// ///cout<<"directory.maxPower="
//<<directory.maxPower<<endl;
//
// directory.maxPower +=
-// directory.prefetchb.l_ip.num_search_ports*directory.prefetchb.local_result.power.searchOp.dynamic*clockRate;
+//directory.prefetchb.l_ip.num_search_ports*directory.prefetchb.local_result.power.searchOp.dynamic*clockRate;
// ///cout<<"directory.maxPower="
//<<directory.maxPower<<endl;
//
// directory.maxPower +=
-// directory.wbb.l_ip.num_search_ports*directory.wbb.local_result.power.searchOp.dynamic*clockRate;
+//directory.wbb.l_ip.num_search_ports*directory.wbb.local_result.power.searchOp.dynamic*clockRate;
//
// cc.power.readOp.dynamic =
-// directory.maxPower*scktRatio*8;//8 is the memory controller counts
+//directory.maxPower*scktRatio*8;//8 is the memory controller counts
// cc.power.readOp.leakage =
-// directory.caches.local_result.power.readOp.leakage +
+//directory.caches.local_result.power.readOp.leakage +
// directory.missb.local_result.power.readOp.leakage
//+
// directory.ifb.local_result.power.readOp.leakage
@@ -1216,27 +1215,27 @@ void SharedCache::displayEnergy(uint32_t indent, bool is_tdp) {
//<<directory1.maxPower<<endl;
//
// directory1.maxPower +=
-// directory1.missb.l_ip.num_search_ports*directory1.missb.local_result.power.searchOp.dynamic*clockRate;
+//directory1.missb.l_ip.num_search_ports*directory1.missb.local_result.power.searchOp.dynamic*clockRate;
// ///cout<<"directory1.maxPower="
//<<directory1.maxPower<<endl;
//
// directory1.maxPower +=
-// directory1.ifb.l_ip.num_search_ports*directory1.ifb.local_result.power.searchOp.dynamic*clockRate;
+//directory1.ifb.l_ip.num_search_ports*directory1.ifb.local_result.power.searchOp.dynamic*clockRate;
// ///cout<<"directory1.maxPower="
//<<directory1.maxPower<<endl;
//
// directory1.maxPower +=
-// directory1.prefetchb.l_ip.num_search_ports*directory1.prefetchb.local_result.power.searchOp.dynamic*clockRate;
+//directory1.prefetchb.l_ip.num_search_ports*directory1.prefetchb.local_result.power.searchOp.dynamic*clockRate;
// ///cout<<"directory1.maxPower="
//<<directory1.maxPower<<endl;
//
// directory1.maxPower +=
-// directory1.wbb.l_ip.num_search_ports*directory1.wbb.local_result.power.searchOp.dynamic*clockRate;
+//directory1.wbb.l_ip.num_search_ports*directory1.wbb.local_result.power.searchOp.dynamic*clockRate;
//
// cc1.power.readOp.dynamic =
-// directory1.maxPower*scktRatio*64/XML->sys.domain_size;
+//directory1.maxPower*scktRatio*64/XML->sys.domain_size;
// cc1.power.readOp.leakage =
-// directory1.caches.local_result.power.readOp.leakage +
+//directory1.caches.local_result.power.readOp.leakage +
// directory1.missb.local_result.power.readOp.leakage
//+
// directory1.ifb.local_result.power.readOp.leakage
@@ -1248,26 +1247,26 @@ void SharedCache::displayEnergy(uint32_t indent, bool is_tdp) {
// cc1.area.set_area(directory1.area*64/XML->sys.domain_size);
//
// cout<<"CC
-// area="<<(cc.area.get_area()+cc1.area.get_area())*1e-6<<endl;
+//area="<<(cc.area.get_area()+cc1.area.get_area())*1e-6<<endl;
// cout<<"CC Power="<<cc.power.readOp.dynamic +
-// cc1.power.readOp.dynamic <<endl;
+//cc1.power.readOp.dynamic <<endl;
// ccTot.area.set_area((cc.area.get_area()+cc1.area.get_area())*1e-6);
// ccTot.power = cc.power + cc1.power;
// }
// else if (XML->sys.first_level_dir==1)
// {
// inv_dir.maxPower =
-// inv_dir.caches.local_result.power.searchOp.dynamic*clockRate*XML->sys.domain_size;
+//inv_dir.caches.local_result.power.searchOp.dynamic*clockRate*XML->sys.domain_size;
// cc1.power.readOp.dynamic =
-// inv_dir.maxPower*scktRatio*(64/XML->sys.domain_size);
+//inv_dir.maxPower*scktRatio*(64/XML->sys.domain_size);
// cc1.power.readOp.leakage =
-// inv_dir.caches.local_result.power.readOp.leakage*inv_dir.caches.l_ip.nbanks*XML->sys.domain_size;
+//inv_dir.caches.local_result.power.readOp.leakage*inv_dir.caches.l_ip.nbanks*XML->sys.domain_size;
//
// cc1.area.set_area(inv_dir.area*64/XML->sys.domain_size);
// cout<<"CC
-// area="<<(cc.area.get_area()+cc1.area.get_area())*1e-6<<endl;
+//area="<<(cc.area.get_area()+cc1.area.get_area())*1e-6<<endl;
// cout<<"CC Power="<<cc.power.readOp.dynamic +
-// cc1.power.readOp.dynamic <<endl;
+//cc1.power.readOp.dynamic <<endl;
// ccTot.area.set_area((cc.area.get_area()+cc1.area.get_area())*1e-6);
// ccTot.power = cc.power + cc1.power;
//
diff --git a/src/gpuwattch/technology_xeon_core.cc b/src/gpuwattch/technology_xeon_core.cc
index 561f5b5..11bb28e 100644
--- a/src/gpuwattch/technology_xeon_core.cc
+++ b/src/gpuwattch/technology_xeon_core.cc
@@ -1904,8 +1904,8 @@ void init_tech_params(double technology, bool is_tag) {
g_tp.min_w_nmos_ = 3 * g_ip->F_sz_um / 2;
g_tp.max_w_nmos_ = 100 * g_ip->F_sz_um;
- g_tp.w_iso = 12.5 * g_ip->F_sz_um; // was 10 micron for the 0.8 micron
- // process
+ g_tp.w_iso = 12.5 * g_ip->F_sz_um; // was 10 micron for the 0.8 micron
+ // process
g_tp.w_sense_n = 3.75 * g_ip->F_sz_um; // sense amplifier N-trans; was 3
// micron for the 0.8 micron process
g_tp.w_sense_p = 7.5 * g_ip->F_sz_um; // sense amplifier P-trans; was 6
diff --git a/src/gpuwattch/xmlParser.cc b/src/gpuwattch/xmlParser.cc
index 375236f..810e6fb 100644
--- a/src/gpuwattch/xmlParser.cc
+++ b/src/gpuwattch/xmlParser.cc
@@ -765,9 +765,9 @@ static const char XML_gbk_big5_ByteTable[256] = {
2, 2, 2, 2, 2, 2, 2, 2,
2, 2, 2, 2, 2, 2, 2, 1 // 0xf0
};
-static const char *XML_ByteTable =
- (const char *)XML_utf8ByteTable; // the default is
-// "characterEncoding=XMLNode::encoding_UTF8"
+static const char *XML_ByteTable = (const char *)
+ XML_utf8ByteTable; // the default is
+ // "characterEncoding=XMLNode::encoding_UTF8"
#endif
XMLNode XMLNode::emptyXMLNode;
diff --git a/src/gpuwattch/xmlParser.h b/src/gpuwattch/xmlParser.h
index caee181..64f5515 100644
--- a/src/gpuwattch/xmlParser.h
+++ b/src/gpuwattch/xmlParser.h
@@ -391,7 +391,7 @@ typedef struct XMLDLLENTRY XMLNode {
*/
static XMLCSTR getError(XMLError error); ///< this gives you a user-friendly
- /// explanation of the parsing error
+ ///explanation of the parsing error
/// Create an XML string starting from the current XMLNode.
XMLSTR createXMLString(int nFormat = 1, int *pnSize = NULL) const;
@@ -426,23 +426,23 @@ typedef struct XMLDLLENTRY XMLNode {
XMLNode getParentNode() const; ///< return the parent node
XMLNode getChildNode(int i = 0) const; ///< return ith child node
XMLNode getChildNode(XMLCSTR name, int i) const; ///< return ith child node
- /// with specific name
- ///(return an empty node if
- /// failing). If i==-1, this
- /// returns the last XMLNode
- /// with the given name.
+ ///with specific name
+ ///(return an empty node if
+ ///failing). If i==-1, this
+ ///returns the last XMLNode
+ ///with the given name.
XMLNode getChildNode(XMLCSTR name, int *i = NULL) const; ///< return next
- /// child node with
- /// specific name
- ///(return an empty
- /// node if failing)
+ ///child node with
+ ///specific name
+ ///(return an empty
+ ///node if failing)
XMLNode getChildNodeWithAttribute(XMLCSTR tagName, XMLCSTR attributeName,
XMLCSTR attributeValue = NULL,
int *i = NULL) const; ///< return child
- /// node with specific
- /// name/attribute
- ///(return an empty
- /// node if failing)
+ ///node with specific
+ ///name/attribute
+ ///(return an empty
+ ///node if failing)
XMLNode getChildNodeByPath(XMLCSTR path, char createNodeIfMissing = 0,
XMLCHAR sep = '/');
///< return the first child node with specific path
@@ -459,21 +459,21 @@ typedef struct XMLDLLENTRY XMLNode {
char isAttributeSet(XMLCSTR name)
const; ///< test if an attribute with a specific name is given
XMLCSTR getAttribute(XMLCSTR name, int i) const; ///< return ith attribute
- /// content with specific
- /// name (return a NULL if
- /// failing)
+ ///content with specific
+ ///name (return a NULL if
+ ///failing)
XMLCSTR getAttribute(XMLCSTR name, int *i = NULL) const; ///< return next
- /// attribute content
- /// with specific
- /// name (return a
- /// NULL if failing)
+ ///attribute content
+ ///with specific
+ ///name (return a
+ ///NULL if failing)
int nAttribute() const; ///< nbr of attribute
XMLClear getClear(int i = 0) const; ///< return ith clear field (comments)
int nClear() const; ///< nbr of clear field
XMLNodeContents enumContents(XMLElementPosition i)
const; ///< enumerate all the different contents (attribute,child,text,
- /// clear) of the current XMLNode. The order is reflecting the
- /// order of the original file/string. NOTE: 0 <= i < nElement();
+ ///clear) of the current XMLNode. The order is reflecting the
+ ///order of the original file/string. NOTE: 0 <= i < nElement();
int nElement() const; ///< nbr of different contents for current node
char isEmpty() const; ///< is this node Empty?
char isDeclaration() const; ///< is this node a declaration <? .... ?>
@@ -515,10 +515,10 @@ typedef struct XMLDLLENTRY XMLNode {
XMLElementPosition pos = -1); ///< Add a new child node
XMLNode addChild(XMLNode nodeToAdd,
XMLElementPosition pos = -1); ///< If the "nodeToAdd" has
- /// some parents, it will be
- /// detached from it's parents
- /// before being attached to
- /// the current XMLNode
+ ///some parents, it will be
+ ///detached from it's parents
+ ///before being attached to
+ ///the current XMLNode
XMLAttribute *addAttribute(XMLCSTR lpszName,
XMLCSTR lpszValuev); ///< Add a new attribute
XMLCSTR addText(XMLCSTR lpszValue,
@@ -539,41 +539,41 @@ typedef struct XMLDLLENTRY XMLNode {
XMLCSTR updateName(XMLCSTR lpszName); ///< change node's name
XMLAttribute *updateAttribute(XMLAttribute *newAttribute,
XMLAttribute *oldAttribute); ///< if the
- /// attribute to
- /// update is
- /// missing, a new
- /// one will be
- /// added
+ ///attribute to
+ ///update is
+ ///missing, a new
+ ///one will be
+ ///added
XMLAttribute *updateAttribute(XMLCSTR lpszNewValue,
XMLCSTR lpszNewName = NULL,
int i = 0); ///< if the attribute to update is
- /// missing, a new one will be added
+ ///missing, a new one will be added
XMLAttribute *updateAttribute(XMLCSTR lpszNewValue, XMLCSTR lpszNewName,
XMLCSTR lpszOldName); ///< set lpszNewName=NULL
- /// if you don't want to
- /// change the name of the
- /// attribute if the
- /// attribute to update is
- /// missing, a new one
- /// will be added
+ ///if you don't want to
+ ///change the name of the
+ ///attribute if the
+ ///attribute to update is
+ ///missing, a new one
+ ///will be added
XMLCSTR updateText(XMLCSTR lpszNewValue, int i = 0); ///< if the text to
- /// update is missing, a
- /// new one will be added
+ ///update is missing, a
+ ///new one will be added
XMLCSTR updateText(XMLCSTR lpszNewValue,
XMLCSTR lpszOldValue); ///< if the text to update is
- /// missing, a new one will be added
+ ///missing, a new one will be added
XMLClear *updateClear(XMLCSTR lpszNewContent,
int i = 0); ///< if the clearTag to update is missing,
- /// a new one will be added
+ ///a new one will be added
XMLClear *updateClear(XMLClear *newP, XMLClear *oldP); ///< if the clearTag
- /// to update is
- /// missing, a new one
- /// will be added
+ ///to update is
+ ///missing, a new one
+ ///will be added
XMLClear *updateClear(XMLCSTR lpszNewValue,
XMLCSTR lpszOldValue); ///< if the clearTag to update
- /// is missing, a new one will be
- /// added
- /** @} */
+ ///is missing, a new one will be
+ ///added
+ /** @} */
/** @defgroup xmlDelete Deleting Nodes or Attributes
* @ingroup xmlModify
@@ -589,33 +589,33 @@ typedef struct XMLDLLENTRY XMLNode {
void deleteAttribute(
int i = 0); ///< Delete the ith attribute of the current XMLNode
void deleteAttribute(XMLCSTR lpszName); ///< Delete the attribute with the
- /// given name (the "strcmp" function
- /// is used to find the right
- /// attribute)
+ ///given name (the "strcmp" function
+ ///is used to find the right
+ ///attribute)
void deleteAttribute(XMLAttribute *anAttribute); ///< Delete the attribute
- /// with the name
- ///"anAttribute->lpszName"
- ///(the "strcmp" function is
- /// used to find the right
- /// attribute)
+ ///with the name
+ ///"anAttribute->lpszName"
+ ///(the "strcmp" function is
+ ///used to find the right
+ ///attribute)
void deleteText(
int i = 0); ///< Delete the Ith text content of the current XMLNode
void deleteText(XMLCSTR lpszValue); ///< Delete the text content "lpszValue"
- /// inside the current XMLNode (direct
- ///"pointer-to-pointer" comparison is
- /// used to find the right text)
+ ///inside the current XMLNode (direct
+ ///"pointer-to-pointer" comparison is
+ ///used to find the right text)
void deleteClear(
int i = 0); ///< Delete the Ith clear tag inside the current XMLNode
void deleteClear(XMLCSTR lpszValue); ///< Delete the clear tag "lpszValue"
- /// inside the current XMLNode (direct
- ///"pointer-to-pointer" comparison is
- /// used to find the clear tag)
- void deleteClear(XMLClear *p); ///< Delete the clear tag "p" inside the
- /// current XMLNode (direct
+ ///inside the current XMLNode (direct
+ ///"pointer-to-pointer" comparison is
+ ///used to find the clear tag)
+ void deleteClear(XMLClear *p); ///< Delete the clear tag "p" inside the
+ ///current XMLNode (direct
///"pointer-to-pointer" comparison on the
- /// lpszName of the clear tag is used to find
- /// the clear tag)
- /** @} */
+ ///lpszName of the clear tag is used to find
+ ///the clear tag)
+ /** @} */
/** @defgroup xmlWOSD ???_WOSD functions.
* @ingroup xmlModify
@@ -666,49 +666,49 @@ typedef struct XMLDLLENTRY XMLNode {
XMLCSTR updateName_WOSD(XMLSTR lpszName); ///< change node's name
XMLAttribute *updateAttribute_WOSD(XMLAttribute *newAttribute,
XMLAttribute *oldAttribute); ///< if the
- /// attribute
- /// to update
- /// is
- /// missing, a
- /// new one
- /// will be
- /// added
+ ///attribute
+ ///to update
+ ///is
+ ///missing, a
+ ///new one
+ ///will be
+ ///added
XMLAttribute *updateAttribute_WOSD(XMLSTR lpszNewValue,
XMLSTR lpszNewName = NULL,
int i = 0); ///< if the attribute to
- /// update is missing, a new
- /// one will be added
+ ///update is missing, a new
+ ///one will be added
XMLAttribute *updateAttribute_WOSD(XMLSTR lpszNewValue, XMLSTR lpszNewName,
XMLCSTR lpszOldName); ///< set
- /// lpszNewName=NULL
- /// if you don't want
- /// to change the
- /// name of the
- /// attribute if the
- /// attribute to
- /// update is
- /// missing, a new
- /// one will be added
+ ///lpszNewName=NULL
+ ///if you don't want
+ ///to change the
+ ///name of the
+ ///attribute if the
+ ///attribute to
+ ///update is
+ ///missing, a new
+ ///one will be added
XMLCSTR updateText_WOSD(XMLSTR lpszNewValue, int i = 0); ///< if the text to
- /// update is
- /// missing, a new
- /// one will be added
+ ///update is
+ ///missing, a new
+ ///one will be added
XMLCSTR updateText_WOSD(XMLSTR lpszNewValue,
XMLCSTR lpszOldValue); ///< if the text to update is
- /// missing, a new one will be
- /// added
+ ///missing, a new one will be
+ ///added
XMLClear *updateClear_WOSD(XMLSTR lpszNewContent,
int i = 0); ///< if the clearTag to update is
- /// missing, a new one will be added
+ ///missing, a new one will be added
XMLClear *updateClear_WOSD(XMLClear *newP,
XMLClear *oldP); ///< if the clearTag to update is
- /// missing, a new one will be
- /// added
+ ///missing, a new one will be
+ ///added
XMLClear *updateClear_WOSD(XMLSTR lpszNewValue,
XMLCSTR lpszOldValue); ///< if the clearTag to
- /// update is missing, a new
- /// one will be added
- /** @} */
+ ///update is missing, a new
+ ///one will be added
+ /** @} */
/** @defgroup xmlPosition Position helper functions (use in conjunction with
* the update&add functions
@@ -729,7 +729,7 @@ typedef struct XMLDLLENTRY XMLNode {
XMLElementPosition positionOfChildNode(XMLNode x) const;
XMLElementPosition positionOfChildNode(XMLCSTR name, int i = 0)
const; ///< return the position of the ith childNode with the specified
- /// name if (name==NULL) return the position of the ith childNode
+ ///name if (name==NULL) return the position of the ith childNode
/** @} */
/// Enumeration for XML character encoding.
@@ -970,11 +970,11 @@ typedef struct XMLDLLENTRY ToXMLStringTool {
ToXMLStringTool() : buf(NULL), buflen(0) {}
~ToXMLStringTool();
void freeBuffer(); ///<call this function when you have finished using this
- /// object to release memory used by the internal buffer.
+ ///object to release memory used by the internal buffer.
XMLSTR toXML(XMLCSTR source); ///< returns a pointer to an internal buffer
- /// that contains a XML-encoded string based on
- /// the "source" parameter.
+ ///that contains a XML-encoded string based on
+ ///the "source" parameter.
/** The "toXMLUnSafe" function is deprecated because there is a possibility of
* "destination-buffer-overflow". It converts the string
@@ -1015,16 +1015,16 @@ typedef struct XMLDLLENTRY XMLParserBase64Tool {
XMLParserBase64Tool() : buf(NULL), buflen(0) {}
~XMLParserBase64Tool();
void freeBuffer(); ///< Call this function when you have finished using this
- /// object to release memory used by the internal buffer.
+ ///object to release memory used by the internal buffer.
/**
* @param formatted If "formatted"=true, some space will be reserved for a
* carriage-return every 72 chars. */
static int encodeLength(int inBufLen,
char formatted = 0); ///< return the length of the
- /// base64 string that encodes a
- /// data buffer of size inBufLen
- /// bytes.
+ ///base64 string that encodes a
+ ///data buffer of size inBufLen
+ ///bytes.
/**
* The "base64Encode" function returns a string containing the base64 encoding
@@ -1035,9 +1035,9 @@ typedef struct XMLDLLENTRY XMLParserBase64Tool {
* All returned strings are sharing the same memory space. */
XMLSTR encode(unsigned char *inByteBuf, unsigned int inByteLen,
char formatted = 0); ///< returns a pointer to an internal
- /// buffer containing the base64 string
- /// containing the binary data encoded from
- ///"inByteBuf"
+ ///buffer containing the base64 string
+ ///containing the binary data encoded from
+ ///"inByteBuf"
/// returns the number of bytes which will be decoded from "inString".
static unsigned int decodeSize(XMLCSTR inString, XMLError *xe = NULL);
@@ -1051,9 +1051,9 @@ typedef struct XMLDLLENTRY XMLParserBase64Tool {
* @param inString If "instring" is malformed, NULL will be returned */
unsigned char *decode(XMLCSTR inString, int *outByteLen = NULL,
XMLError *xe = NULL); ///< returns a pointer to an
- /// internal buffer containing the
- /// binary data decoded from
- ///"inString"
+ ///internal buffer containing the
+ ///binary data decoded from
+ ///"inString"
/**
* decodes data from "inString" to "outByteBuf". You need to provide the size
generated by cgit v1.3 (git 2.53.0) at 2026-07-10 23:26:12 +0000