diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/gpgpu-sim/gpu-cache.cc | 15 | ||||
| -rw-r--r-- | src/gpgpu-sim/mem_fetch.h | 2 | ||||
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 6 |
3 files changed, 15 insertions, 8 deletions
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc index 3a5a67d..f4448d3 100644 --- a/src/gpgpu-sim/gpu-cache.cc +++ b/src/gpgpu-sim/gpu-cache.cc @@ -409,6 +409,11 @@ void tag_array::fill(new_addr_type addr, unsigned time, // assert( m_config.m_alloc_policy == ON_FILL ); unsigned idx; enum cache_request_status status = probe(addr, idx, mask, is_write); + + if (status == RESERVATION_FAIL) { + return; + } + bool before = m_lines[idx]->is_modified_line(); // assert(status==MISS||status==SECTOR_MISS); // MSHR should have prevented // redundant memory request @@ -1375,7 +1380,7 @@ enum cache_request_status data_cache::wr_miss_wa_naive( // the evicted block may have wrong chip id when advanced L2 hashing is // used, so set the right chip address from the original mf wb->set_chip(mf->get_tlx_addr().chip); - wb->set_parition(mf->get_tlx_addr().sub_partition); + wb->set_partition(mf->get_tlx_addr().sub_partition); send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events); } @@ -1428,7 +1433,7 @@ enum cache_request_status data_cache::wr_miss_wa_fetch_on_write( // the evicted block may have wrong chip id when advanced L2 hashing is // used, so set the right chip address from the original mf wb->set_chip(mf->get_tlx_addr().chip); - wb->set_parition(mf->get_tlx_addr().sub_partition); + wb->set_partition(mf->get_tlx_addr().sub_partition); send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events); } @@ -1501,7 +1506,7 @@ enum cache_request_status data_cache::wr_miss_wa_fetch_on_write( // the evicted block may have wrong chip id when advanced L2 hashing is // used, so set the right chip address from the original mf wb->set_chip(mf->get_tlx_addr().chip); - wb->set_parition(mf->get_tlx_addr().sub_partition); + wb->set_partition(mf->get_tlx_addr().sub_partition); send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events); } @@ -1568,7 +1573,7 @@ enum cache_request_status data_cache::wr_miss_wa_lazy_fetch_on_read( // the evicted block may have wrong chip id when advanced L2 hashing is // used, so set the right chip address from the original mf wb->set_chip(mf->get_tlx_addr().chip); - wb->set_parition(mf->get_tlx_addr().sub_partition); + wb->set_partition(mf->get_tlx_addr().sub_partition); send_write_request(wb, cache_event(WRITE_BACK_REQUEST_SENT, evicted), time, events); } @@ -1650,7 +1655,7 @@ enum cache_request_status data_cache::rd_miss_base( // the evicted block may have wrong chip id when advanced L2 hashing is // used, so set the right chip address from the original mf wb->set_chip(mf->get_tlx_addr().chip); - wb->set_parition(mf->get_tlx_addr().sub_partition); + wb->set_partition(mf->get_tlx_addr().sub_partition); send_write_request(wb, WRITE_BACK_REQUEST_SENT, time, events); } return MISS; diff --git a/src/gpgpu-sim/mem_fetch.h b/src/gpgpu-sim/mem_fetch.h index e039846..283fe80 100644 --- a/src/gpgpu-sim/mem_fetch.h +++ b/src/gpgpu-sim/mem_fetch.h @@ -77,7 +77,7 @@ class mem_fetch { const addrdec_t &get_tlx_addr() const { return m_raw_addr; } void set_chip(unsigned chip_id) { m_raw_addr.chip = chip_id; } - void set_parition(unsigned sub_partition_id) { + void set_partition(unsigned sub_partition_id) { m_raw_addr.sub_partition = sub_partition_id; } unsigned get_data_size() const { return m_data_size; } diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 6f68283..4013ae9 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -2416,8 +2416,10 @@ void pipelined_simd_unit::cycle() { if (!m_dispatch_reg->dispatch_delay()) { int start_stage = m_dispatch_reg->latency - m_dispatch_reg->initiation_interval; - move_warp(m_pipeline_reg[start_stage], m_dispatch_reg); - active_insts_in_pipeline++; + if(m_pipeline_reg[start_stage]->empty()) { + move_warp(m_pipeline_reg[start_stage], m_dispatch_reg); + active_insts_in_pipeline++; + } } } occupied >>= 1; |