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-rw-r--r--src/cuda-sim/cuda-sim.cc8
-rw-r--r--src/gpgpu-sim/gpu-sim.cc2
-rw-r--r--src/gpgpu-sim/shader.cc10
-rw-r--r--src/gpgpu-sim/shader.h18
4 files changed, 21 insertions, 17 deletions
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 6da0840..506bc95 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -648,8 +648,10 @@ void ptx_instruction::set_opcode_and_latency()
if ( has_memory_write() ) op = STORE_OP;
break;
case LD_OP: op = LOAD_OP; break;
+ case MMA_LD_OP: op = LOAD_OP; break;
case LDU_OP: op = LOAD_OP; break;
case ST_OP: op = STORE_OP; break;
+ case MMA_ST_OP: op = STORE_OP; break;
case BRA_OP: op = BRANCH_OP; break;
case BREAKADDR_OP: op = BRANCH_OP; break;
case TEX_OP: op = LOAD_OP; mem_op=TEX; break;
@@ -897,9 +899,11 @@ void ptx_instruction::pre_decode()
case WB_OPTION: cache_op = CACHE_WRITE_BACK; break;
case WT_OPTION: cache_op = CACHE_WRITE_THROUGH; break;
default:
- if( m_opcode == LD_OP || m_opcode == LDU_OP )
+ //if( m_opcode == LD_OP || m_opcode == LDU_OP )
+ if( m_opcode == MMA_LD_OP || m_opcode == LD_OP || m_opcode == LDU_OP )
cache_op = CACHE_ALL;
- else if( m_opcode == ST_OP )
+ //else if( m_opcode == ST_OP )
+ else if( m_opcode == ST_OP || m_opcode == ST_OP )
cache_op = CACHE_WRITE_BACK;
else if( m_opcode == ATOM_OP )
cache_op = CACHE_GLOBAL;
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index cc23051..3e064c7 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -1541,7 +1541,7 @@ void gpgpu_sim::cycle()
}
}
- if (!(gpu_sim_cycle % 20000)) {
+ if (!(gpu_sim_cycle % 50000)) {
// deadlock detection
if (m_config.gpu_deadlock_detect && gpu_sim_insn == last_gpu_sim_insn) {
gpu_deadlock = true;
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index c01f867..226e7f0 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -1387,7 +1387,7 @@ ldst_unit::process_cache_access( cache_t* cache,
assert( !read_sent );
inst.accessq_pop_back();
if ( inst.is_load() ) {
- for ( unsigned r=0; r < 4; r++)
+ for ( unsigned r=0; r < 8; r++)
if (inst.out[r] > 0)
m_pending_writes[inst.warp_id()][inst.out[r]]--;
}
@@ -1489,7 +1489,7 @@ bool ldst_unit::memory_cycle( warp_inst_t &inst, mem_stage_stall_type &stall_rea
inst.accessq_pop_back();
//inst.clear_active( access.get_warp_mask() );
if( inst.is_load() ) {
- for( unsigned r=0; r < 4; r++)
+ for( unsigned r=0; r < 8; r++)
if(inst.out[r] > 0)
assert( m_pending_writes[inst.warp_id()][inst.out[r]] > 0 );
} else if( inst.is_store() )
@@ -1767,7 +1767,7 @@ void ldst_unit:: issue( register_set &reg_set )
if (inst->is_load() and inst->space.get_type() != shared_space) {
unsigned warp_id = inst->warp_id();
unsigned n_accesses = inst->accessq_count();
- for (unsigned r = 0; r < 4; r++) {
+ for (unsigned r = 0; r < 8; r++) {
unsigned reg_id = inst->out[r];
if (reg_id > 0) {
m_pending_writes[warp_id][reg_id] += n_accesses;
@@ -1789,7 +1789,7 @@ void ldst_unit::writeback()
if( !m_next_wb.empty() ) {
if( m_operand_collector->writeback(m_next_wb) ) {
bool insn_completed = false;
- for( unsigned r=0; r < 4; r++ ) {
+ for( unsigned r=0; r < 8; r++ ) {
if( m_next_wb.out[r] > 0 ) {
if( m_next_wb.space.get_type() != shared_space ) {
assert( m_pending_writes[m_next_wb.warp_id()][m_next_wb.out[r]] > 0 );
@@ -1991,7 +1991,7 @@ void ldst_unit::cycle()
//}
bool pending_requests=false;
- for( unsigned r=0; r<4; r++ ) {
+ for( unsigned r=0; r<8; r++ ) {
unsigned reg_id = pipe_reg.out[r];
if( reg_id > 0 ) {
if( m_pending_writes[warp_id].find(reg_id) != m_pending_writes[warp_id].end() ) {
diff --git a/src/gpgpu-sim/shader.h b/src/gpgpu-sim/shader.h
index b7deae6..90a3134 100644
--- a/src/gpgpu-sim/shader.h
+++ b/src/gpgpu-sim/shader.h
@@ -1224,13 +1224,13 @@ protected:
enum pipeline_stage_name_t {
ID_OC_SP=0,
ID_OC_SFU,
+ ID_OC_TENSOR_CORE,
ID_OC_MEM,
OC_EX_SP,
OC_EX_SFU,
+ OC_EX_TENSOR_CORE,
OC_EX_MEM,
EX_WB,
- ID_OC_TENSOR_CORE,
- OC_EX_TENSOR_CORE,
N_PIPELINE_STAGES
};
@@ -1268,9 +1268,9 @@ struct shader_core_config : public core_config
strcpy(toks,pipeline_widths_string);
toks = strtok(toks,",");
- pipe_widths[OC_EX_TENSOR_CORE]=1;
- pipe_widths[ID_OC_TENSOR_CORE]=1;
- for (unsigned i = 0; i < N_PIPELINE_STAGES-2; i++) {
+ // pipe_widths[OC_EX_TENSOR_CORE]=1;
+ // pipe_widths[ID_OC_TENSOR_CORE]=1;
+ for (unsigned i = 0; i < N_PIPELINE_STAGES; i++) {
assert(toks);
ntok = sscanf(toks,"%d", &pipe_widths[i]);
assert(ntok == 1);
@@ -1286,12 +1286,12 @@ struct shader_core_config : public core_config
max_warps_per_shader = n_thread_per_shader/warp_size;
assert( !(n_thread_per_shader % warp_size) );
max_sfu_latency = 512;
- max_tensor_core_latency = 512;
+ max_tensor_core_latency = 64;
max_sp_latency = 32;
- gpgpu_num_tensor_core_units=1;
+ gpgpu_num_tensor_core_units=8;
gpgpu_operand_collector_num_units_tensor_core=24;
- gpgpu_operand_collector_num_in_ports_tensor_core=1;
- gpgpu_operand_collector_num_out_ports_tensor_core=1;
+ gpgpu_operand_collector_num_in_ports_tensor_core=8;
+ gpgpu_operand_collector_num_out_ports_tensor_core=8;
m_L1I_config.init(m_L1I_config.m_config_string,FuncCachePreferNone);
m_L1T_config.init(m_L1T_config.m_config_string,FuncCachePreferNone);
m_L1C_config.init(m_L1C_config.m_config_string,FuncCachePreferNone);
generated by cgit v1.3 (git 2.53.0) at 2026-07-11 02:18:37 +0000