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The block containing predicate ret instruction should add the
consecutive block to its successor_ids set. next_addr should be assigned
with current instruction address add instruction size instead of 1.
Signed-off-by: Mengchi Zhang <[email protected]>
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support for CUDA 8.0 PTX
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shfl instruction implemented
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Initial support of CUDA Dynamic Parallelism on GPGPUSim
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memory mapping, turn off by default
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initiation_interval numbers for bsmad
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to complete the TODOs noted in bsmad_impl
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in its warp
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Now, sst_impl doesn't functionally execute on the last indexed element of an array, but instead on the actual last thread that executes
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sst_impl
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of elements instead of the device memory address
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in sstarr memory
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are in the sstarr memory and writes the data back into sstarr memory.
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shader, should use hw_cta_id to store shared mem info
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distributor directly
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your custom inserted PTX with CPTX_BEGIN and CPTX_END, respectively.
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