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this gives us a place to stick caches shared among shader cores but
on the shader side of the interconnect... maybe move the clock
boundary code here? after integrating booksim 2 code?
2. added a pending write table to ldst_unit rather than scoreboard
... rationale is that ld/st unit needs to process register writes
once it is done it can notify scoreboard once.
3. re-enabled shared memory delay (use pipeline within ldst_unit)
4. re-enabling operand collector writeback for all instruction types
5. disable MSHRs in this change list
passing CUDA 3.1 regression
next? texture cache, then redo mshrs?
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845]
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2. refactor memory stage into a ld/st function unit
3. refactor memory access generation (moved into warp_inst_t class)
the above should make supporting fermi uarch much easier
passing CUDA 3.1 regression
still need to...
(a) update scoreboard to keep count of outstanding memory requests
and use operand collector for writebacks into register file
(b) add back shared memory pipeline delay
(c) remove use of MSHR's for non-cached global/local accesses
(d) replace texture cache with a split tag/data array pipe
(e) re-implement memory_partition stuff so it makes more sense
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7844]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7835]
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1. Moving mem_access_t to abstract_hardware_model and making set (queue) of
accesses part of warp_inst_t. I.e., treat set of accesses as an ISA concept
rather than a hardware organization concept. This is only partly "done"...
logic for computing accesses is still part of shader_core_ctx in this CL.
Given number of warp_inst_t accessors for accessq, now seems like we might even
want to move some memory stage code into warp_inst_t class. How those
accesses make it to memory system is the hardware concept.
2. Making warp_inst_t an explicit arguement of subroutines used in memory stage...
The eventual goal here is (likely) to refactor memory into a hardware block...
i.e., have function units be a class that contains some set of pipeline stages
internally and some set of input/output "ports".
3. Moving accessor functions is_load, is_store; is_const, is_local into class
declaration (where they belong).
4. Removing code for selecting pipeline uarch (might add it back later, but first
want a clean GT200 organization). In particular, removing option to have an
operand collector -- now you MUST have the operand collector.
5. Removing more deadcode from prior changes (fixed delay queue related)
Scripts/configs:
6. Correlation script not printing out exit condition when hardware launch fails
7. Update config files to have proper compute model selected
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7834]
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entirely)
2. some bug fixes for warp_inst_t
3. creating a new class, gpgpu_t, which contains the functional "memory" state visible
to all threads running on a GPU (doing this as part of my continuing effort to hunt
down and eradicate every global variable that is not the top level "the gpu")
4. other misc. changes
Almost passing CUDA 3.1 regression? oclHistogram keeps failing under torque, but
does not fail when run on the command line from the same directory.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7827]
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refactoring: create warp_inst_t that provides notion of a group of scalar instructions
traveling down the pipeline.
delete DWF
delete MIMD
delete warp_tracker
delete old writeback stage, replace it with a stub that just writes back everything
delete old pipeline model
current status: MSHR's need to change to deal with the new structure
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7814]
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