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2018-11-03merged with memory subsytem. Regression is passing but tensorcore kernel is ↵aamir
stuck in deadlock
2018-11-02added incount and outcount, addressed all of the pull request commentsaamir
2018-10-24merged tensor-cores codeaamir
2018-09-16print for mem transactionaamir
2018-09-09minor changes for generating mem transaction in timing model. NOTE NOT COMPLETEDaamir
2018-08-16Timing model for VCOREnegargoli93
2018-07-21merging the changes of cutlass on negar tensorcore branchaamir
2018-06-20Tensor core timing modelnegargoli93
2018-05-30changes for vector operandsaamir
2018-05-12commit for eece527projectnegargoli93
2018-03-28fix compile errors on Ubuntu LTS 16.04Tor Aamodt
2017-09-24Changed how warp level instructions are handled to avoid an assert that is ↵speverel
guaranteed to fail in functional simulation only mode. Hopefully this shouldn't introduce any new issues.
2017-08-17Merged all work on the dev branch since the divergence point into the dnn ↵speverel
branch, incorporating Dynamic Parallelism and many bug fixes.
2016-09-06Merge pull request #30 from sspenst/devgpgpu-sim
shfl instruction implemented
2016-09-05Merge pull request #28 from jwang323/cdp_cleangpgpu-sim
Initial support of CUDA Dynamic Parallelism on GPGPUSim
2016-08-24Added shfl instructionsspenst
2016-08-08Forgot to multiply by the synapsesspenst
2016-08-05Deleted useless commentssspenst
2016-08-05Added ptx_warp_info to know how many threads within a warp have executedsspenst
2016-08-04A thread executing BSMAD is now able to access information from all threads ↵sspenst
in its warp
2016-07-11Reverted the previous commit to add a cleaner way of getting NUM_THREADS. ↵sspenst
Now, sst_impl doesn't functionally execute on the last indexed element of an array, but instead on the actual last thread that executes
2016-07-08Made gridDim and blockDim global variables so that they can be accessed from ↵sspenst
sst_impl
2016-07-07SST instruction now updates the original array instead of storing the result ↵sspenst
in sstarr memory
2016-07-06Added sstarr memory, which works the same as shared memorysspenst
2016-07-06ADD: add kernel launching latency from stream to distributorJin Wang
2016-07-06ADD: add stats for kernel launching and complete cycleJin Wang
2016-07-06ADD: add cdp latencyJin Wang
2016-07-05ADD: delete streams created by cta when deleting kernelJin Wang
2016-07-05BUG: multiple child kernels finishJin Wang
2016-07-05BUG: do not handle cudaGetParameterBufferV2 and cudaLaunchDeviceV2 as ↵Jin Wang
call.uni in reconvergence
2016-07-05MOD: add child kernel stream and scheduling supportJin Wang
2016-06-07Added support for cudaMemcpyDefault flag in cudaMemcpy. Also increased the ↵speverel
maximum allowable memory to 2GB and the compute version to 5.2.
2015-03-04initial support for CUDA 5.0, 5.5, 6.0 to get template from SDK runningAhmed ElTantawy
2014-08-14Support for named bariers + bar.red + bar.arrive instructionsAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18452]
2014-08-14Fix Bug 81Ahmed El-Shafiey
http://www.gpgpu-sim.org/bugs/show_bug.cgi?id=81 Review ID: 173001 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18179]
2014-08-14Review 77001: Fixing Writeback/Write allocate hard coded memory_access_types ↵Tayler Hetherington
for specific caches. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16683]
2014-08-14Adding option to force global memory accesses to skip L1 data cache while ↵Wilson Fung
still caching data from local memory space. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16601]
2014-08-14Adding the ability to querry the WARPSZ flag from the ptx script.Tim Rogers
Also changed some initialization code when cores are created in both the funcational and perfromance simulator review:3001 lgtm:5 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16506]
2014-08-14Interconnection traffic breakdown stats (integration from TM branch).Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16495]
2014-08-14Fixing bug 59 + cleaning some code related to the power modelAhmed El-Shafiey
Review ID:32001 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16205]
2014-08-14make sure L1 cache is flushed at a configuration change between kernels, ↵Ahmed El-Shafiey
even if flushing L1 cache between kernels option is not set [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15834]
2014-08-14 - Adding support for cudaFuncSetCacheConfig API, that allows changing theAhmed El-Shafiey
L1 Cache and Shared Memory configurations across kernels. The support enable the user to specify two more configurations (Preferred L1) or (Preferred Shared Memory) besides the default config. If the cudaFuncSetCacheConfig API is used to set the cache configuration of a specific kernel to either of these configuration (cudaFuncCachePreferShared, cudaFuncCachePreferL1), the simulator will change the cache configuration at kernel launch accordingly, if there is no alternative configurations provided to the simulator it will use the default configurations with a warning message display [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15816]
2014-08-14Replaced the legacy L2 cache access stats with more meaningful breakdown ↵Wilson Fung
that categorize access by their access type (global memory read/write, local memory read/write, instruction read, ... etc.). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15784]
2014-08-14MergingTim Rogers
//depot/gpgpu_sim_research/fermi_locality/... to //depot/gpgpu_sim_research/fermi/... Adding in some protected constructors to the core cache classes. This allows us to customize caches (for example having them use a custom tag array) more easily. Also I made the in-class tag_array object in the baseline_cache into a pointer. This allows derived classes to easily create custom tag arrays. I think in general, class extendibility is increased when pointers are used instead of in-object storage. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15223]
2014-08-14Fix for bug 30 (external).Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14789]
2014-08-14Merging Power model into FermiTayler Hetherington
//depot/gpgpu_sim_research/fermi_power/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]
2014-08-14OpenCL newer diver fixHadi Jooybar
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14554]
2014-08-14Fixed the shared memory bank conflict model for GTX 480 and Tesla C2050. ↵Wilson Fung
Now the two configs will feature 32-bank shared memory with a more flexible broadcast mechanism. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14509]
2014-08-14Modified the cache hierarchy, reorganized code to eliminate code ↵Tayler Hetherington
replication, implemented write allocate / write back policies in L2 cache, added configurable parameters in gpgpusim.config ("W" = Write Allocate, "N" = No write allocate -> "P" = Private, "S" = shared), modified the cache configuration lines to always be separated by ":" instead of ":" and ",", and modified L1 and L2 data cache to be "Write Back" caches instead of "Read Only". Still need to implement Ahmed's sectored cache implementation. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14081]
2014-08-14Minor refactoring for the SIMT Stack implementation and fixing some indentationWilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14067]
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