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authoraamir <[email protected]>2018-09-09 15:10:06 -0700
committeraamir <[email protected]>2018-09-09 15:10:06 -0700
commit7a77d951e6a900d61436df12826bb677aeaee6e6 (patch)
treec60e6ad27d4f4da273fdd8ceeae633b17e0e0273 /src/abstract_hardware_model.h
parent242f3fd369f6ea3f0e808dd5d6446a294e63d9aa (diff)
minor changes for generating mem transaction in timing model. NOTE NOT COMPLETED
Diffstat (limited to 'src/abstract_hardware_model.h')
-rw-r--r--src/abstract_hardware_model.h8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 781509f..9c418fa 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -81,6 +81,10 @@ enum uarch_op_t {
VP_CORE_OP,
ALU_SFU_OP,
LOAD_OP,
+ VP_LOAD_OP,
+ TENSOR_CORE_LOAD_OP,
+ TENSOR_CORE_STORE_OP,
+ VP_STORE_OP,
STORE_OP,
BRANCH_OP,
BARRIER_OP,
@@ -801,8 +805,8 @@ public:
{
fprintf(fp," [inst @ pc=0x%04x] ", pc );
}
- bool is_load() const { return (op == LOAD_OP || memory_op == memory_load); }
- bool is_store() const { return (op == STORE_OP || memory_op == memory_store); }
+ bool is_load() const { return (op == LOAD_OP ||op==TENSOR_CORE_LOAD_OP||op==VP_LOAD_OP || memory_op == memory_load); }
+ bool is_store() const { return (op == STORE_OP ||op==TENSOR_CORE_STORE_OP||op==VP_STORE_OP || memory_op == memory_store); }
unsigned get_num_operands() const {return num_operands;}
unsigned get_num_regs() const {return num_regs;}
void set_num_regs(unsigned num) {num_regs=num;}