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Also changed some initialization code when cores are created in both the funcational and perfromance simulator
review:3001 lgtm:5
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review:28002 lgtm:0
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//depot/gpgpu_sim_research/fermi_tim/...
to //depot/gpgpu_sim_research/fermi/...
Integrating CLs up to 15295. Descriptions of these CL's are included.
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A couple changes to aeriel-vision for warp issue plot support
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More arielvision changes to support the variable-entry length stacked bar chart
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Properly printing the right resolution of dynamic warp ids
***.
Generalized the scheduler code and added detailed statistics for which warps issue each cycle.
Verified the execution of the LRR scheduler - still have to get the two level scheduler to work.
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Implementing the 2lvl scehduler has it has been originally coded.
LRR on both the inner and outer levels
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Adding in a debug tracing system to GPGPU-Sim.
I am sick of writing debug code - then having to comment out, ifdef out or delete it to checkin.
This also allows for print streams so the user can decided which traces they would like to see.
Every print in GPGPU-Sim should go through this system - then it will be really easy to only get the information you want and more importantly people will (a) write and (b) checkin code that actually profiles what they are building.
Reading tracefiles is superiour in many ways to single stepping since you can print the world and just vet the logfile for what you need.
This also fascilitates advice from the Debugging Rules! book which states that you should never throw away a debugging tool. Having debug prints that don't get thrown away is big.
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Allowing the trace to be specified in the Make.
Run Make TRACE=0 to compile the code without any traces
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Allowing prints from the performance sim to get the actual ptx instruction text
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Getting the two level scheduler to actaully work...
What is released in fermi does not work at all - it effectively performs "static warp limit" from my CCWS paper.
Warps are never demoted from the active list since the functionality checking to see if they are waiting on a longop is completly broken.
Maybe if the original author had access to the tracing functions this would not have happened.
The islongop test was completely broken. It did not mark the register as used, it marked the register number in the instruction as used.
For example if this instruction was creating a long op:
ld r6 [r1]
It would mark register 0 as waiting for a long op (since it is register 0 of the two registers in this instruction), not register 6.
Additionally, whenever ANY instruction from a warp releases registers, ALL the longops being tracked for this warp get cleared....
The only way anyone ever thought this worked is if they did not test it....
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Reworking the warp schedulers to share common code.
Making the GTX480 use gto by default. I am not sure wht they really use, but it really can't be LRR.
Also adding in a new file for custom shared trace defines. These are useful when you want a print that has some
additional criteria or information printed.
Verified that the schedulers all work to a first order based on traces.
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Making it so you can run the stats collection scripts from any directory.
Also allow the caller to specify a stats file instead of just assume its always the same one
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The observed latencies are reduced by 5 to account for other stages in the SM pipeline
Eventually this should be calibrated against the microbenchmarks
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Merging
//depot/gpgpu_sim_research/fermi_ayoub/distribution/src/cuda-sim/cuda-sim.cc
//depot/gpgpu_sim_research/fermi_ayoub/distribution/src/cuda-sim/cuda-sim.h
//depot/gpgpu_sim_research/fermi_ayoub/distribution/src/cuda-sim/instructions.cc
//depot/gpgpu_sim_research/fermi_ayoub/distribution/src/cuda-sim/ptx_sim.h
to //depot/gpgpu_sim_research/fermi/distribution/src/cuda-sim/...
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update README and CHANGES to hopefully anticipate most basic questions we'll see
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Parameters are finalized at kernel launch, which means the contents
of parameter memory are initialized. Kernel arguement names have a
fixed order, hence same address should be assigned on subsequent
kernel launches of same kernel in other streams provided the data size
param_t::size of arguments for each kernel launch is identical (an
assertion has been added to check this is true).
- passing regression
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OpenCL)
This changelist adds full support for streams supported by a new class,
stream_manager and enables concurrent execution of kernels from different
streams.
- fast_regression.sh fails for simpleMultiCopy, simpleStreams (other tests
passing)
** Known issues **
- Kernel parameter passing is not done correctly for concurrent kernel execution
(somehow concurrentKernels is not affected by this): the parameters are
stored inside function_info, which is shared among parallel kernel launches
so that the values passed into the launch are likely to get overwritten if
multiple grids are launched in parallel streams.
- Statistics are printed out whenever the simulation thread runs out of
cuda commands (doesn't make sense to print out when a kernel ends during
concurrent kernel execution). This will probably require further tweaking
so as to be more compatible with data collection scripts.
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configuration
components of this class.
2. clock memory pipeline no. subwarp times for each shader clock and increase
rob-size for texture cache (trying to improve correlation, currently at 0.9218)
3. start to modify shader stats to add back features for visualizer (warp
divergence distribution kind of working again)
passing cuda 3.1 regression and ptxplus correlation tests
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entirely)
2. some bug fixes for warp_inst_t
3. creating a new class, gpgpu_t, which contains the functional "memory" state visible
to all threads running on a GPU (doing this as part of my continuing effort to hunt
down and eradicate every global variable that is not the top level "the gpu")
4. other misc. changes
Almost passing CUDA 3.1 regression? oclHistogram keeps failing under torque, but
does not fail when run on the command line from the same directory.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7827]
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refactoring: create warp_inst_t that provides notion of a group of scalar instructions
traveling down the pipeline.
delete DWF
delete MIMD
delete warp_tracker
delete old writeback stage, replace it with a stub that just writes back everything
delete old pipeline model
current status: MSHR's need to change to deal with the new structure
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cache)
2. update gpgpusim.config for Quadro to use L1 cache geometry from Henry's ISPASS paper
3. minor edit to CUDA api : add notion of fat_cubin_handle (currently not used for anything)
4. minor edits to deadlock detection message (more accurate reporting of source of deadlock)
5. other minor edits
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7809]
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(i'll use "fermi" for more disruptive changes to the pipeline model such
as updating the MSHRs and getting rid of the warp tracker, ripping out DWF, etc...)
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this integrates the ptxplus functional model changes, but has only been
verified with CUDA 3.1 PTX regressions (which pass)
still need to verify ptxplus itself is working in this branch
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(add scoreboard logic from ptxplus branch and modified operand collector
with parallel ALU/SFU pipelines)
passing regressions
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changes required to do this (this enables oclReduction SDK 3.1 to pass
and is a prerequisite to Fermi style concurrent kernel launching)
- separate kernel launch for cuda and opencl (and init_grid functions)
- add pgm_info structure for holding kernel function_info pointer in
_cl_program object after ptx compilation
** added support for clEnqueueNDRangeKernel with local_work_size==NULL
which is part of OpenCL spec and used in oclSortingNetworks (however,
this is a braindead implementation that only handles the case where
global_work_size[0] is smaller than the max number of threads per
shader; moreover oclSortingNetworks is still not working but for what
looks like another reason)
** refactoring / cleanup
- g_global_symbol_table made static to ptx_parser.cc
- remove g_kernel_name_to_symtab_lookup (not really being used)
- moving various function prototypes into headers (e.g., if foo() defined
in bar.cc, then place prototype in bar.h)
- adding icnt_reg_options()
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