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2025-08-19running formatter (#126)JRPan
* running formatter * consolidate CI runs * use cluster to run formatter * use cluster to run formatter * Add a CI-Success step
2025-02-18A bunch of maintenance fixes, the largest of which is getting the PTX ↵Tim Rogers
simulation to work with CUDA 12. (#95) * Fixing the formatter to always use a consistent format and running it on the codebase * Update linux-so-version.txt * Update Makefile * A couple of unnecessary files that are lingering around * Support CUDA 12 * Getting the PTX simulations to work with CUDA 12. The issue is that ptxas added more information (number of barriers and compile time). We have to parse these or lexx/yacc fail. * Update ptxinfo.l debug MACRO was ineffective * Update gpgpusim_check.cmake Update to make the CUDA version print a warning, not an error and updating the print to be more reflective of what the actual problem is.
2019-09-13Big reformat change using clang-format-6.0Nick
2019-09-13Revert "Add src/cuda-sim formatting"Nick
This reverts commit 0c023e41809dba8897c37af6bb03e5c3aa9ebc5e.
2019-09-13Add src/cuda-sim formattingNick
2019-07-15Move s_g_pc_to_insnMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-15Move g_debug_pcMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-11Move g_ptx_thread_info_uid_nextMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-11Move g_ptx_thread_info_delete_countMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-11Move ptx_tex_regsMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-11Move g_ptx_cta_info_sm_idx_usedMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-11Move g_override_embedded_ptxMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-10Move g_debug_thread_uidMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-10Move g_assemble_code_next_pcMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-10Move cdp_latencyMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-10Move gpgpu_ptx_instruction_classificationMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-10Move g_pc_to_finfoMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-10Move g_globals and g_constantsMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-10Move g_inst_classification_stat and g_inst_op_classification_statMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-10Move g_cuda_launch_blockingMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-09Move g_rptsMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-09Move gpgpu_param_num_shadersMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-09Move g_ptx_sim_modeMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-09Move g_global_name_lookup and g_constant_name_lookupMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-09Move g_ptx_kernel_countMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-09Move some more varsMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-09Move opcode_initiation_*Mengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-09Move opcode_latency_*Mengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-08Move g_ptx_sim_num_insnMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-08Move g_ptxinfo_error_detectedMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-08Move cp_cta_resumeMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-08Move cp_countMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-08Move opcode_latency_int thus pass gpgpu_context into many classesMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-04-11adding local xbar and fast execution modeMahmoud
2018-11-09changes for checkpoint supportDeval Shah
2018-06-21WIP adding support for PTX JIT and dumping params to cudaLaunchesJonathan
2015-03-04initial support for CUDA 5.0, 5.5, 6.0 to get template from SDK runningAhmed ElTantawy
2014-08-14Adding the ability to querry the WARPSZ flag from the ptx script.Tim Rogers
Also changed some initialization code when cores are created in both the funcational and perfromance simulator review:3001 lgtm:5 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16506]
2014-08-14Fixing the broken valgrind build.Tim Rogers
review:28002 lgtm:0 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15957]
2014-08-14MergingTim Rogers
//depot/gpgpu_sim_research/fermi_tim/... to //depot/gpgpu_sim_research/fermi/... Integrating CLs up to 15295. Descriptions of these CL's are included. *** A couple changes to aeriel-vision for warp issue plot support *** More arielvision changes to support the variable-entry length stacked bar chart *** Properly printing the right resolution of dynamic warp ids ***. Generalized the scheduler code and added detailed statistics for which warps issue each cycle. Verified the execution of the LRR scheduler - still have to get the two level scheduler to work. *** Implementing the 2lvl scehduler has it has been originally coded. LRR on both the inner and outer levels *** Adding in a debug tracing system to GPGPU-Sim. I am sick of writing debug code - then having to comment out, ifdef out or delete it to checkin. This also allows for print streams so the user can decided which traces they would like to see. Every print in GPGPU-Sim should go through this system - then it will be really easy to only get the information you want and more importantly people will (a) write and (b) checkin code that actually profiles what they are building. Reading tracefiles is superiour in many ways to single stepping since you can print the world and just vet the logfile for what you need. This also fascilitates advice from the Debugging Rules! book which states that you should never throw away a debugging tool. Having debug prints that don't get thrown away is big. *** Allowing the trace to be specified in the Make. Run Make TRACE=0 to compile the code without any traces *** Allowing prints from the performance sim to get the actual ptx instruction text *** Getting the two level scheduler to actaully work... What is released in fermi does not work at all - it effectively performs "static warp limit" from my CCWS paper. Warps are never demoted from the active list since the functionality checking to see if they are waiting on a longop is completly broken. Maybe if the original author had access to the tracing functions this would not have happened. The islongop test was completely broken. It did not mark the register as used, it marked the register number in the instruction as used. For example if this instruction was creating a long op: ld r6 [r1] It would mark register 0 as waiting for a long op (since it is register 0 of the two registers in this instruction), not register 6. Additionally, whenever ANY instruction from a warp releases registers, ALL the longops being tracked for this warp get cleared.... The only way anyone ever thought this worked is if they did not test it.... *** Reworking the warp schedulers to share common code. Making the GTX480 use gto by default. I am not sure wht they really use, but it really can't be LRR. Also adding in a new file for custom shared trace defines. These are useful when you want a print that has some additional criteria or information printed. Verified that the schedulers all work to a first order based on traces. *** Making it so you can run the stats collection scripts from any directory. Also allow the caller to specify a stats file instead of just assume its always the same one [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15296]
2014-08-14Adding configurable instruction latencies and initiation intervalsAndrew M. B. Boktor
The observed latencies are reduced by 5 to account for other stages in the SM pipeline Eventually this should be calibrated against the microbenchmarks [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12310]
2014-08-14Integrating the pure functional simulationAyub Gubran
Merging //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/cuda-sim/cuda-sim.cc //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/cuda-sim/cuda-sim.h //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/cuda-sim/instructions.cc //depot/gpgpu_sim_research/fermi_ayoub/distribution/src/cuda-sim/ptx_sim.h to //depot/gpgpu_sim_research/fermi/distribution/src/cuda-sim/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11288]
2014-08-14fixup some dangling referencesTor Aamodt
update README and CHANGES to hopefully anticipate most basic questions we'll see [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9880]
2014-08-14change copyright notice to include authorsTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9872]
2011-06-29changing copyright to BSDTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9687]
2010-12-28- parameter memory and active threads now part of kernel_info_t:Tor Aamodt
Parameters are finalized at kernel launch, which means the contents of parameter memory are initialized. Kernel arguement names have a fixed order, hence same address should be assigned on subsequent kernel launches of same kernel in other streams provided the data size param_t::size of arguments for each kernel launch is identical (an assertion has been added to check this is true). - passing regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8303]
2010-12-28- Checkpointing new support for concurrent kernel execution (CUDA only, not ↵Tor Aamodt
OpenCL) This changelist adds full support for streams supported by a new class, stream_manager and enables concurrent execution of kernels from different streams. - fast_regression.sh fails for simpleMultiCopy, simpleStreams (other tests passing) ** Known issues ** - Kernel parameter passing is not done correctly for concurrent kernel execution (somehow concurrentKernels is not affected by this): the parameters are stored inside function_info, which is shared among parallel kernel launches so that the values passed into the launch are likely to get overwritten if multiple grids are launched in parallel streams. - Statistics are printed out whenever the simulation thread runs out of cuda commands (doesn't make sense to print out when a kernel ends during concurrent kernel execution). This will probably require further tweaking so as to be more compatible with data collection scripts. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8302]
2010-11-30integrate changes (makes code more modular, i would argue)Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8179]
2010-10-241. adding top level configuration class and making shader and memory ↵Tor Aamodt
configuration components of this class. 2. clock memory pipeline no. subwarp times for each shader clock and increase rob-size for texture cache (trying to improve correlation, currently at 0.9218) 3. start to modify shader stats to add back features for visualizer (warp divergence distribution kind of working again) passing cuda 3.1 regression and ptxplus correlation tests [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7909]
2010-10-09refactoring: moving texture reference mappings into gpgpu_t Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7835]
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