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2019-05-17Move ptx parser to reentrantMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2018-11-09resolving merge conflictDeval Shah
2018-11-03merged with memory subsytem. Regression is passing but tensorcore kernel is ↵aamir
stuck in deadlock
2018-10-24merged tensor-cores codeaamir
2018-08-14parsing changes for timing modelaamir
2018-08-09added loadaamir
2018-08-07implemented prmt and started working on variable precision mul instaamir
2018-06-21WIP adding support for PTX JIT and dumping params to cudaLaunchesJonathan
2018-06-11added all the configurationaamir
2018-06-05parse all ptx and add to symbol tableJonathan
2018-06-05added support for wmma:load_c:f16_typeaamir
2018-05-27added wmma parsing but execution getting abortedaamir
2018-04-01fix regressions -- move call to pre_decode into do_pdomTor Aamodt
2018-03-27support for pinned memories - temporary fixAmruth
2018-03-23dynamic pdom analysis at runtimeAmruth
2017-05-09Fix next block addr to link predicate ret block to consecutive blockMengchi Zhang
The block containing predicate ret instruction should add the consecutive block to its successor_ids set. next_addr should be assigned with current instruction address add instruction size instead of 1. Signed-off-by: Mengchi Zhang <[email protected]>
2016-09-06Merge pull request #30 from sspenst/devgpgpu-sim
shfl instruction implemented
2016-09-05Merge pull request #28 from jwang323/cdp_cleangpgpu-sim
Initial support of CUDA Dynamic Parallelism on GPGPUSim
2016-08-24Added shfl instructionsspenst
2016-07-06ADD: add separate cdp latencyJin Wang
2016-07-06ADD: add cdp latencyJin Wang
2016-07-05MOD: compute child parameter sizeJin Wang
2016-07-05ADD: add support for cudaStreamCreateWithFlagsJin Wang
2016-07-05BUG: do not handle cudaGetParameterBufferV2 and cudaLaunchDeviceV2 as ↵Jin Wang
call.uni in reconvergence
2016-07-05ADD: initial support for instruction group used by CDPJin Wang
2016-06-07The ptx parser now recognizes the NC option for ld.global, however this ↵sspenst
option is not actually implemented
2016-06-02Added handling of .cc option for arithmetic instructions. NOTE: Only made ↵speverel
changes to parse instructions. Carry functionality NOT fully implemented; .cc instructions function like their unmodified ueqivelents. Also modified GTX750Ti config to model L1 data cache as simply not being used for global loads (instead of not existing at all). Changed ptxinfo parsing to avoid crashing when info includes texture information.
2015-06-05Fixing bug with local stats not being reset on call to update_stats. Added ↵Tayler Hetherington
code to remove the trailing newline character from the C++ name de-mangling fix. Also, fixed small bug with previous commit
2015-06-05Fixing bug with max cycle/instruction/cta + bug with C++ name de-mangling ↵Tayler Hetherington
with spaces (e.g., using templates)
2015-03-04initial support for CUDA 5.0, 5.5, 6.0 to get template from SDK runningAhmed ElTantawy
2014-08-14This should fix 2.3 regression and may fix others as well.Ahmed El-Shafiey
Remove redudant definition for some tokens which confuses the parser [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18462]
2014-08-14Support for named bariers + bar.red + bar.arrive instructionsAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18452]
2014-08-14Okay, both the crash and the valgrind complaint are caused by the non-type ↵Tim Rogers
safeness of fprintf. Fix is to explicitly tell fprintf that the to_string.c_str() result is a string. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15312]
2014-08-14Fixed at least one error in the valgrind build. Forgot to initial a member ↵Tim Rogers
variable. I thought the init() function where dynamic_warp_id is initialized was called on construction. It is not. Added a default value in the constructor. Maybe a code review would have caught this :) Also cleaned up some weird code I had in the ptx_instruction::to_string(). Also trimmed out tabs from our stored source line string so it is much more readable on print [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15310]
2014-08-14Fixing a bug exposed by the fix for bug 42.Tim Rogers
The "_" "null" register potentially generated by ptx and intentionally generated by ptxplus was being initialized without a type. This caused the parser to think it was not a register. Fix is to allow the parser to think of it as register, but ensure the arch-sim does not by adding a flag indicating that it is special. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15305]
2014-08-14MergingTim Rogers
//depot/gpgpu_sim_research/fermi_tim/... to //depot/gpgpu_sim_research/fermi/... Integrating CLs up to 15295. Descriptions of these CL's are included. *** A couple changes to aeriel-vision for warp issue plot support *** More arielvision changes to support the variable-entry length stacked bar chart *** Properly printing the right resolution of dynamic warp ids ***. Generalized the scheduler code and added detailed statistics for which warps issue each cycle. Verified the execution of the LRR scheduler - still have to get the two level scheduler to work. *** Implementing the 2lvl scehduler has it has been originally coded. LRR on both the inner and outer levels *** Adding in a debug tracing system to GPGPU-Sim. I am sick of writing debug code - then having to comment out, ifdef out or delete it to checkin. This also allows for print streams so the user can decided which traces they would like to see. Every print in GPGPU-Sim should go through this system - then it will be really easy to only get the information you want and more importantly people will (a) write and (b) checkin code that actually profiles what they are building. Reading tracefiles is superiour in many ways to single stepping since you can print the world and just vet the logfile for what you need. This also fascilitates advice from the Debugging Rules! book which states that you should never throw away a debugging tool. Having debug prints that don't get thrown away is big. *** Allowing the trace to be specified in the Make. Run Make TRACE=0 to compile the code without any traces *** Allowing prints from the performance sim to get the actual ptx instruction text *** Getting the two level scheduler to actaully work... What is released in fermi does not work at all - it effectively performs "static warp limit" from my CCWS paper. Warps are never demoted from the active list since the functionality checking to see if they are waiting on a longop is completly broken. Maybe if the original author had access to the tracing functions this would not have happened. The islongop test was completely broken. It did not mark the register as used, it marked the register number in the instruction as used. For example if this instruction was creating a long op: ld r6 [r1] It would mark register 0 as waiting for a long op (since it is register 0 of the two registers in this instruction), not register 6. Additionally, whenever ANY instruction from a warp releases registers, ALL the longops being tracked for this warp get cleared.... The only way anyone ever thought this worked is if they did not test it.... *** Reworking the warp schedulers to share common code. Making the GTX480 use gto by default. I am not sure wht they really use, but it really can't be LRR. Also adding in a new file for custom shared trace defines. These are useful when you want a print that has some additional criteria or information printed. Verified that the schedulers all work to a first order based on traces. *** Making it so you can run the stats collection scripts from any directory. Also allow the caller to specify a stats file instead of just assume its always the same one [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15296]
2014-08-14Fixed the timing model for LDU instruction, before it was not recognized as ↵Wilson Fung
a memory instruction in the timing model. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14538]
2014-08-14Fixing regression failure: vote.all was broken by vote.ballet implementation.Wilson Fung
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13996]
2014-08-14Added implementation of vote.ballot (passing directed test). Added popc ↵Wilson Fung
(not tested). Reducing number of iterations for radixSortThrust for regression. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13993]
2014-08-14Copied in Arun's SIMT stack fix for recursive calls (CL8574)Inderpreet Singh
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13410]
2014-08-14- print out instructions at branch divergence/reconvergence points (more ↵Tor Aamodt
informative) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13399]
2014-08-14- adding clearer documentation to setup_environmentTor Aamodt
- removing an assert that gets triggered when using CUDA 4.2 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12865]
2014-08-14Fixing bug 126. Now DXTC runs to completion by not giving correct result ↵Wilson Fung
(expected). The key is that the missing function is now in place. Also removed reference to print_shader_cycle_distro() (this is deprecated by AerialVision). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 11346]
2014-08-14change copyright notice to include authorsTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9872]
2011-06-29changing copyright to BSDTor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9687]
2010-12-20fix from CL 8285Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8287]
2010-12-15Added next instruction type to ptxplus, ".ff64". It's the same as ".f64" ↵Jimmy Kwa
except it reads and stores from two adjacent registers instead of a single 64 bit register. ".ff64" instructions are now printed in decuda_to_ptxplus. Support in the simulator for ".ff64" has been added but it is untested. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8278]
2010-11-30integrate changes (makes code more modular, i would argue)Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8179]
2010-10-241. updates to .gdbinit fileTor Aamodt
2. update texture to bypass ROP-delay queue... correlation now 0.9592 [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7912]
2010-10-241. adding top level configuration class and making shader and memory ↵Tor Aamodt
configuration components of this class. 2. clock memory pipeline no. subwarp times for each shader clock and increase rob-size for texture cache (trying to improve correlation, currently at 0.9218) 3. start to modify shader stats to add back features for visualizer (warp divergence distribution kind of working again) passing cuda 3.1 regression and ptxplus correlation tests [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7909]
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