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path: root/src/cuda-sim/ptx_ir.h
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2018-11-09resolving merge conflictDeval Shah
2018-11-03merged with memory subsytem. Regression is passing but tensorcore kernel is ↵aamir
stuck in deadlock
2018-10-24merged tensor-cores codeaamir
2018-08-16Timing model for VCOREnegargoli93
2018-08-16fix alignment bug in parser, modified ptxjitconfig, minor fixesJonathan
2018-08-07implemented prmt and started working on variable precision mul instaamir
2018-08-07working fix for deadlock due to operand collector, parser changes to support ↵J
culaunchkernel
2018-07-22added regression and debugged the failing testcaseaamir
2018-07-18added c++filt that works better, param offset dumping, protection for ↵Jonathan
failing system calls
2018-07-04dumps ptx kernels and scripts to launch all kernelsJonathan
2018-07-04dump and load block and grid size and launchJonathan
2018-06-28dumps pointers by accessing global memoryJonathan
2018-06-28Tests to find conditions that a value is a pointer and new mallocPtr_SizeJonathan
2018-06-27WIP dump paramsJonathan
2018-06-21WIP adding support for PTX JIT and dumping params to cudaLaunchesJonathan
2018-06-14bfe bug fixJonathan
2018-06-11added all the configurationaamir
2018-06-05added support for wmma:load_c:f16_typeaamir
2018-05-31mma_ld_implaamir
2018-05-30adding code for wmma_ld_impl, error at decode spaceaamir
2018-05-30changes for vector operandsaamir
2018-05-27added wmma parsing but execution getting abortedaamir
2018-05-12commit for eece527projectnegargoli93
2018-04-22Some classes were referred to as a class and a struct (reported as clang ↵Nathan Conrad
warnings). This makes these consistent.
2018-04-19Crash when array pointers are passedAmruth
2018-04-14solving alignment issueAmruth
2018-04-01fix regressions -- move call to pre_decode into do_pdomTor Aamodt
2018-03-23dynamic pdom analysis at runtimeAmruth
2017-08-17Merged all work on the dev branch since the divergence point into the dnn ↵speverel
branch, incorporating Dynamic Parallelism and many bug fixes.
2016-09-06Merge pull request #30 from sspenst/devgpgpu-sim
shfl instruction implemented
2016-08-24Added shfl instructionsspenst
2016-07-06Added sstarr memory, which works the same as shared memorysspenst
2016-07-06BUG: wrong declaration for m_args_aligned_sizeJin Wang
2016-07-05MOD: compute child parameter sizeJin Wang
2016-07-05ADD: add cudaGetParameterBufferV2 and add cudaLaunchDeviceV2 implementation. ↵Jin Wang
Kernel launch to stream not yet implemented
2016-07-05ADD: initial support for instruction group used by CDPJin Wang
2015-03-04initial support for CUDA 5.0, 5.5, 6.0 to get template from SDK runningAhmed ElTantawy
2014-08-14This should fix 2.3 regression and may fix others as well.Ahmed El-Shafiey
Remove redudant definition for some tokens which confuses the parser [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18462]
2014-08-14Support for named bariers + bar.red + bar.arrive instructionsAhmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18452]
2014-08-14This should fix the NNC undefined memory locations bug. It turned out that ↵Ahmed El-Shafiey
the main problem is in the benchmark code itself. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15537]
2014-08-14fixing some assignment in the "get_operand_value" function where unsigned ↵Ahmed El-Shafiey
were assigned to unions! Also, do proper initialization in the constructors of operand_info, therse among places where valgrind complaining from NNC, but still it is not fixed. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15503]
2014-08-14Fixing a bug exposed by the fix for bug 42.Tim Rogers
The "_" "null" register potentially generated by ptx and intentionally generated by ptxplus was being initialized without a type. This caused the parser to think it was not a register. Fix is to allow the parser to think of it as register, but ensure the arch-sim does not by adding a flag indicating that it is special. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15305]
2014-08-14MergingTim Rogers
//depot/gpgpu_sim_research/fermi_tim/... to //depot/gpgpu_sim_research/fermi/... Integrating CLs up to 15295. Descriptions of these CL's are included. *** A couple changes to aeriel-vision for warp issue plot support *** More arielvision changes to support the variable-entry length stacked bar chart *** Properly printing the right resolution of dynamic warp ids ***. Generalized the scheduler code and added detailed statistics for which warps issue each cycle. Verified the execution of the LRR scheduler - still have to get the two level scheduler to work. *** Implementing the 2lvl scehduler has it has been originally coded. LRR on both the inner and outer levels *** Adding in a debug tracing system to GPGPU-Sim. I am sick of writing debug code - then having to comment out, ifdef out or delete it to checkin. This also allows for print streams so the user can decided which traces they would like to see. Every print in GPGPU-Sim should go through this system - then it will be really easy to only get the information you want and more importantly people will (a) write and (b) checkin code that actually profiles what they are building. Reading tracefiles is superiour in many ways to single stepping since you can print the world and just vet the logfile for what you need. This also fascilitates advice from the Debugging Rules! book which states that you should never throw away a debugging tool. Having debug prints that don't get thrown away is big. *** Allowing the trace to be specified in the Make. Run Make TRACE=0 to compile the code without any traces *** Allowing prints from the performance sim to get the actual ptx instruction text *** Getting the two level scheduler to actaully work... What is released in fermi does not work at all - it effectively performs "static warp limit" from my CCWS paper. Warps are never demoted from the active list since the functionality checking to see if they are waiting on a longop is completly broken. Maybe if the original author had access to the tracing functions this would not have happened. The islongop test was completely broken. It did not mark the register as used, it marked the register number in the instruction as used. For example if this instruction was creating a long op: ld r6 [r1] It would mark register 0 as waiting for a long op (since it is register 0 of the two registers in this instruction), not register 6. Additionally, whenever ANY instruction from a warp releases registers, ALL the longops being tracked for this warp get cleared.... The only way anyone ever thought this worked is if they did not test it.... *** Reworking the warp schedulers to share common code. Making the GTX480 use gto by default. I am not sure wht they really use, but it really can't be LRR. Also adding in a new file for custom shared trace defines. These are useful when you want a print that has some additional criteria or information printed. Verified that the schedulers all work to a first order based on traces. *** Making it so you can run the stats collection scripts from any directory. Also allow the caller to specify a stats file instead of just assume its always the same one [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15296]
2014-08-14proposed fix for bug 42 (Alexander Samoilov)Tor Aamodt
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15271]
2014-08-14Merging Power model into FermiTayler Hetherington
//depot/gpgpu_sim_research/fermi_power/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]
2014-08-14Extended PTX parser to recognize the .ptr .shared directive and allocate ↵Wilson Fung
shared memory buffer to those pointers. This is required to support OpenCL local memorywith the newer NVIDIA driver. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14565]
2014-08-14Fixed the timing model for LDU instruction, before it was not recognized as ↵Wilson Fung
a memory instruction in the timing model. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14538]
2014-08-14Added implementation of vote.ballot (passing directed test). Added popc ↵Wilson Fung
(not tested). Reducing number of iterations for radixSortThrust for regression. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13993]
2014-08-14Fixing bugs 169, 170, 171Ahmed El-Shafiey
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13761]
2014-08-14Fixing compile error on my machineAndrew M. B. Boktor
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 13703]