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path: root/src/gpgpu-sim/gpu-sim.h
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2019-09-13Seems like multiple passes for reformatting commentsNick
2019-09-13Big reformat change using clang-format-6.0Nick
2019-09-13Revert "Add src/gpgpu-sim formatting"Nick
This reverts commit 9c9b1341613e767f306b2b73b5b8a5317b6ee563.
2019-09-13Revert "Add additional formatting pass on directories"Nick
This reverts commit ca563ea85ead434e0d579026b5e66e829af5efe5.
2019-09-13Add additional formatting pass on directoriesNick
2019-09-13Add src/gpgpu-sim formattingNick
2019-08-30Making the max cycles/inst counters 64 bitstgrogers
2019-08-23fixing CUDA 10 failMahmoud
2019-08-22Merge branch 'dev' of https://github.com/purdue-aalp/gpgpu-sim_distribution ↵Mahmoud
into dev-private
2019-07-29adding simple dram modelMahmoud
2019-07-15adding the new elapsed_cycles_sm_tot statsMahmoud
2019-07-14Move sm_next_access_uidMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-11Move g_watchpoint_hitsMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-08Move g_ptx_sim_num_insnMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-08Move cp_countMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-08Move opcode_latency_int thus pass gpgpu_context into many classesMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-03Remove g_filenameMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-07-03Add backward pointer to gpgpu_simMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2019-06-05adding new cuda 9 APIs to run the deepbench workloadsMahmoud
2019-05-16fixing the link symbol errorMahmoud
2019-05-15make gpu_tot_cycle local variable not global variableMahmoud
2019-05-02Merge branch 'dev' of https://github.com/gpgpu-sim/gpgpu-sim_distribution ↵Mahmoud
into dev
2019-04-18changes for compute capabiltyPreyesh Dalmia
2019-04-17Adding configs for device limits and fixed other misc bugsSuchita Pati
2019-04-11adding some stats and random hashingMahmoud
2018-11-09changes for checkpoint supportDeval Shah
2018-11-09resolving merge conflictDeval Shah
2018-10-09Adding in an occupancy metric to match the nvprof metrictgrogers
2018-10-07Unrolling Aksahy's stats - as they seem to be really screwing things up.tgrogers
2018-05-01Added support for -gpgpu_registers_per_block configSuchita Pati
2018-04-10added config -gpgpu_shmem_per_block and fixed cudaGetDeviceAttributes functionSuchita Pati
2018-03-22Change 252 by jain156@akshayj-lt1 on 2017/05/29 10:51:32Akshay Jain
Checking in the data footprint stats as reported in the micro paper. The implementation uses gpgpu pointer, due to which I don't feel fine pushing to mainline. May be I can do the stats check and increment in l2cache.cc through a public function to avoid exposing gpgpu pointer to public
2017-11-18fixing a stupid inheritance bugtgrogers
2017-11-18Making the perf sim copy optional, getting rid of an assert that will happen ↵tgrogers
with the new hack and incrementing the cycle so that cudamemcopies take some time (if we don't do this the LRU in the cache does not work)
2017-11-18vectoradd is successfully filling the l2tgrogers
2017-10-30adding new stats and change the PascalP100-HBM configMahmoud
2017-10-27add more statistics and chaging Pascal configMahmoud
2017-10-26Changing the Titan X config file to use the last modificationsMahmoud
2017-10-25The commits includes:Mahmoud
1- REEAD/WERITE buffer for DRAM 2- Fixing FETCH_ON_WRITE cahce policy bug
2017-09-12Adding HBM modelMahmoud
2017-07-20Fixing BankGroup Indexing BugMahmoud
2017-07-12Fixing BankGroup Indexing BugMahmoud
2016-07-05MOD: add child kernel stream and scheduling supportJin Wang
2015-06-05Fixing bug with max cycle/instruction/cta + bug with C++ name de-mangling ↵Tayler Hetherington
with spaces (e.g., using templates)
2014-08-14Redesigned the memory partition unit to support multiple L2 cache banks per ↵Wilson Fung
partition. Each L2 cache banks has its own connection to the interconnection network to allow L2 bandwidth to scale without increase the number of memory parttiion units. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16613]
2014-08-14Adding new option '-liveness_message_freq', which throttles the frequency of ↵Wilson Fung
simulation liveness printout (default to 1 per second in wall clock time). [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16482]
2014-08-14Review: 33001. Updating/cleaning up the cache statistics. Moving the ↵Tayler Hetherington
statistics from the tag array to the cache access functions. Added cache_stats class to record all memory accesses and access outcomes to each cache. Removed L2CacheAccessBreakdown_t. Cleaned up power_stats to reflect changes in the cache stats. Updated the cache stats printing. This will cause the performance gold files to change as the output format has been changed. [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16452]
2014-08-14make sure L1 cache is flushed at a configuration change between kernels, ↵Ahmed El-Shafiey
even if flushing L1 cache between kernels option is not set [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15834]
2014-08-14 - Adding support for cudaFuncSetCacheConfig API, that allows changing theAhmed El-Shafiey
L1 Cache and Shared Memory configurations across kernels. The support enable the user to specify two more configurations (Preferred L1) or (Preferred Shared Memory) besides the default config. If the cudaFuncSetCacheConfig API is used to set the cache configuration of a specific kernel to either of these configuration (cudaFuncCachePreferShared, cudaFuncCachePreferL1), the simulator will change the cache configuration at kernel launch accordingly, if there is no alternative configurations provided to the simulator it will use the default configurations with a warning message display [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15816]
2014-08-14MergingTim Rogers
//depot/gpgpu_sim_research/fermi_tim/... to //depot/gpgpu_sim_research/fermi/... Integrating CLs up to 15295. Descriptions of these CL's are included. *** A couple changes to aeriel-vision for warp issue plot support *** More arielvision changes to support the variable-entry length stacked bar chart *** Properly printing the right resolution of dynamic warp ids ***. Generalized the scheduler code and added detailed statistics for which warps issue each cycle. Verified the execution of the LRR scheduler - still have to get the two level scheduler to work. *** Implementing the 2lvl scehduler has it has been originally coded. LRR on both the inner and outer levels *** Adding in a debug tracing system to GPGPU-Sim. I am sick of writing debug code - then having to comment out, ifdef out or delete it to checkin. This also allows for print streams so the user can decided which traces they would like to see. Every print in GPGPU-Sim should go through this system - then it will be really easy to only get the information you want and more importantly people will (a) write and (b) checkin code that actually profiles what they are building. Reading tracefiles is superiour in many ways to single stepping since you can print the world and just vet the logfile for what you need. This also fascilitates advice from the Debugging Rules! book which states that you should never throw away a debugging tool. Having debug prints that don't get thrown away is big. *** Allowing the trace to be specified in the Make. Run Make TRACE=0 to compile the code without any traces *** Allowing prints from the performance sim to get the actual ptx instruction text *** Getting the two level scheduler to actaully work... What is released in fermi does not work at all - it effectively performs "static warp limit" from my CCWS paper. Warps are never demoted from the active list since the functionality checking to see if they are waiting on a longop is completly broken. Maybe if the original author had access to the tracing functions this would not have happened. The islongop test was completely broken. It did not mark the register as used, it marked the register number in the instruction as used. For example if this instruction was creating a long op: ld r6 [r1] It would mark register 0 as waiting for a long op (since it is register 0 of the two registers in this instruction), not register 6. Additionally, whenever ANY instruction from a warp releases registers, ALL the longops being tracked for this warp get cleared.... The only way anyone ever thought this worked is if they did not test it.... *** Reworking the warp schedulers to share common code. Making the GTX480 use gto by default. I am not sure wht they really use, but it really can't be LRR. Also adding in a new file for custom shared trace defines. These are useful when you want a print that has some additional criteria or information printed. Verified that the schedulers all work to a first order based on traces. *** Making it so you can run the stats collection scripts from any directory. Also allow the caller to specify a stats file instead of just assume its always the same one [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15296]
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