diff options
| author | Mahmoud <[email protected]> | 2017-10-30 20:23:51 -0400 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2017-10-30 20:23:51 -0400 |
| commit | 0b1a646c0ddf5d4db64a2b6fe9dfa30789cf1cd4 (patch) | |
| tree | e13ad4e06b8106f9797bb910448ff4cc833ac46c /src/gpgpu-sim/gpu-sim.h | |
| parent | f23021ad8663636e1103bd75a742480cb6238435 (diff) | |
adding new stats and change the PascalP100-HBM config
Diffstat (limited to 'src/gpgpu-sim/gpu-sim.h')
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/gpgpu-sim/gpu-sim.h b/src/gpgpu-sim/gpu-sim.h index 043fcee..c04648c 100644 --- a/src/gpgpu-sim/gpu-sim.h +++ b/src/gpgpu-sim/gpu-sim.h @@ -198,8 +198,14 @@ struct memory_config { bk_tag_length = i-1; assert(nbkgrp>0 && "Number of bank groups cannot be zero"); tRCDWR = tRCD-(WL+1); + if(elimnate_rw_turnaround) + { + tRTW = 0; + tWTR = 0; + } else { tRTW = (CL+(BL/data_command_freq_ratio)+2-WL); tWTR = (WL+(BL/data_command_freq_ratio)+tCDLR); + } tWTP = (WL+(BL/data_command_freq_ratio)+tWR); dram_atom_size = BL * busW * gpu_n_mem_per_ctrlr; // burst length x bus width x # chips per partition @@ -266,6 +272,8 @@ struct memory_config { unsigned nbk; + bool elimnate_rw_turnaround; + unsigned data_command_freq_ratio; // frequency ratio between DRAM data bus and command bus (2 for GDDR3, 4 for GDDR5) unsigned dram_atom_size; // number of bytes transferred per read or write command |