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This reverts commit 9c9b1341613e767f306b2b73b5b8a5317b6ee563.
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1. Decouple the constructor of interconnect interface
2. Some type changed to unsigned from int
Fixed Bug: wrong variable in InterconnectInterface::Busy()
Review: 83001
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16877]
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Details: See Review 80001 https://gpgpu-sim-code-review.appspot.com/80001/
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16747]
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//depot/gpgpu_sim_research/fermi_power/distribution/...
to //depot/gpgpu_sim_research/fermi/distribution/...
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9872]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9687]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8153]
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configuration
components of this class.
2. clock memory pipeline no. subwarp times for each shader clock and increase
rob-size for texture cache (trying to improve correlation, currently at 0.9218)
3. start to modify shader stats to add back features for visualizer (warp
divergence distribution kind of working again)
passing cuda 3.1 regression and ptxplus correlation tests
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7909]
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this gives us a place to stick caches shared among shader cores but
on the shader side of the interconnect... maybe move the clock
boundary code here? after integrating booksim 2 code?
2. added a pending write table to ldst_unit rather than scoreboard
... rationale is that ld/st unit needs to process register writes
once it is done it can notify scoreboard once.
3. re-enabled shared memory delay (use pipeline within ldst_unit)
4. re-enabling operand collector writeback for all instruction types
5. disable MSHRs in this change list
passing CUDA 3.1 regression
next? texture cache, then redo mshrs?
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845]
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(i'll use "fermi" for more disruptive changes to the pipeline model such
as updating the MSHRs and getting rid of the warp tracker, ripping out DWF, etc...)
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7805]
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changes required to do this (this enables oclReduction SDK 3.1 to pass
and is a prerequisite to Fermi style concurrent kernel launching)
- separate kernel launch for cuda and opencl (and init_grid functions)
- add pgm_info structure for holding kernel function_info pointer in
_cl_program object after ptx compilation
** added support for clEnqueueNDRangeKernel with local_work_size==NULL
which is part of OpenCL spec and used in oclSortingNetworks (however,
this is a braindead implementation that only handles the case where
global_work_size[0] is smaller than the max number of threads per
shader; moreover oclSortingNetworks is still not working but for what
looks like another reason)
** refactoring / cleanup
- g_global_symbol_table made static to ptx_parser.cc
- remove g_kernel_name_to_symtab_lookup (not really being used)
- moving various function prototypes into headers (e.g., if foo() defined
in bar.cc, then place prototype in bar.h)
- adding icnt_reg_options()
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7168]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 6829]
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