weft - CPEN 511 Project - Weft: Improving SIMD Utilization through MIMD-like Co-issue and Thread Compaction

Age	Commit message (Collapse)	Author
2014-08-14	change copyright notice to include authors	Tor Aamodt
	[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9872]
2011-06-29	changing copyright to BSD	Tor Aamodt
	[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 9687]
2010-11-28	enabling L2 data cache... it is write through, write evict like L1.	Tor Aamodt
	[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 8154]
2010-10-21	1. rewriting memory access generation code (from scratch), why not...	Tor Aamodt
	passing CUDA 3.1 and ptxplus correlation, but correlation still bad (0.62)... after debugging 1 to get it working with ptxplus, problem is very clear: shared and constant cache accesses not occuring for operations that combine these with ALU operations. TODO: have a "read-operands" stage, which somehow combines operand collector register reading with shared and const memory accesses... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7895]
2010-10-19	adding texture cache model with fragment fifo for latency hiding	Tor Aamodt
	passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7886]
2010-10-18	Re-designed cache model:	Tor Aamodt
	- read only cache model with integrated mshrs (no L1D, yet); new cache interface should be easily extendable to support texture cache with latency fifo and separate tag/data arrays, though this is not yet added (currently tags and data arrays are not decoupled for texture) - new partition model using the above removes all old MSHRs, L1D etc... passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7875]
2010-10-16	1. moving address decoding into a class (and out of cache entirely)	Tor Aamodt
	2. moving DRAM timing parameters into memory_config class 3. removing some likely useless statistics 4. other cleaning up of code passing CUDA 3.1 regression [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7868]
2010-10-12	1. adding simt_core_cluster, which models a TPC or (for fermi) GPC...	Tor Aamodt
	this gives us a place to stick caches shared among shader cores but on the shader side of the interconnect... maybe move the clock boundary code here? after integrating booksim 2 code? 2. added a pending write table to ldst_unit rather than scoreboard ... rationale is that ld/st unit needs to process register writes once it is done it can notify scoreboard once. 3. re-enabled shared memory delay (use pipeline within ldst_unit) 4. re-enabling operand collector writeback for all instruction types 5. disable MSHRs in this change list passing CUDA 3.1 regression next? texture cache, then redo mshrs? [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845]
2010-10-02	refactor: mem_fetch now a class	Tor Aamodt
	[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7807]
2010-10-02	refactoring: make shd_cache_t into a class (cache_t), plus some other ↵	Tor Aamodt
	cleaning up [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7806]
2010-10-01	integrating recent changes from fermi-test into fermi	Tor Aamodt
	(i'll use "fermi" for more disruptive changes to the pipeline model such as updating the MSHRs and getting rid of the warp tracker, ripping out DWF, etc...) [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7805]
2010-08-08	refactor: moving extern variable declarations into headers	Tor Aamodt
	[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7172]
2010-07-17	- add support for cvta and isspacep instructions (currently assuming	Tor Aamodt
	a fixed address mapping between shared,local to generic that depends upon hardware thread context used... might be interesting to explore tradeoffs at some point) - remove util.h... we don't need TRUE, FALSE anymore now that everything is C++ - remove some dead code from shader_decode [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 6867]
2010-07-15	creating branch for adding support for CUDA 3.x and Fermi	Tor Aamodt
	[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 6829]