| Age | Commit message (Collapse) | Author |
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Added Memory divergence stats
Data shows same divergence characteristics across PTX and PTX+
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branch, incorporating Dynamic Parallelism and many bug fixes.
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1- round robin inst issue for warp multiple schedulers
2- add sector mask in the memory request (to bused later for L2 sector cache)
3- Adding Fermi coalescer
4- Ensure different exen units are used in dual_issue mode
5- Report how many dual_issue happened
6- Adding oldest_first scheduler
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memory mapping, turn off by default
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distributor directly
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with spaces (e.g., using templates)
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initial support for CUDA 5.0, 5.5, 6.0 to get template from SDK running
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to fetch into.
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(should fix regressions).
-remove some printfs that were there for debugging
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18480]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 18452]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 17183]
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Review ID: 89001
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 17086]
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write-allocation policy. Also added description for the write-allocation fix implemented by Tayler.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16914]
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Details: See Review 80001 https://gpgpu-sim-code-review.appspot.com/80001/
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16747]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16671]
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partition. Each L2 cache banks has its own connection to the interconnection network to allow L2 bandwidth to scale without increase the number of memory parttiion units.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16613]
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still caching data from local memory space.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16601]
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Main contribution is a static warp limiting scheduler.
There is also some minor cleanup to the heirarchy of the cache code and removal some excessively long lines
Review ID: 36001 lgtm: 1
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16580]
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"WarpIssueDynamicIdBreakdown" are being printed in the visualization files without any data.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16572]
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Also changed some initialization code when cores are created in both the funcational and perfromance simulator
review:3001 lgtm:5
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16506]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16495]
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regressions butwill cause the correlation to fail due to a change in the output - need to update gold files on failure.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16477]
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for Quadro config).
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16457]
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statistics from the tag array to the cache access functions. Added cache_stats class to record all memory accesses and access outcomes to each cache. Removed L2CacheAccessBreakdown_t. Cleaned up power_stats to reflect changes in the cache stats. Updated the cache stats printing. This will cause the performance gold files to change as the output format has been changed.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16452]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16428]
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Review ID:32001
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16205]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15788]
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counting the number of flits arriving at the cores instead of the number of flits leaving each memory partition.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15746]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15745]
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variable.
I thought the init() function where dynamic_warp_id is initialized was called on construction.
It is not. Added a default value in the constructor. Maybe a code review would have caught this :)
Also cleaned up some weird code I had in the ptx_instruction::to_string().
Also trimmed out tabs from our stored source line string so it is much more readable on print
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15310]
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//depot/gpgpu_sim_research/fermi_tim/...
to //depot/gpgpu_sim_research/fermi/...
Integrating CLs up to 15295. Descriptions of these CL's are included.
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A couple changes to aeriel-vision for warp issue plot support
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More arielvision changes to support the variable-entry length stacked bar chart
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Properly printing the right resolution of dynamic warp ids
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Generalized the scheduler code and added detailed statistics for which warps issue each cycle.
Verified the execution of the LRR scheduler - still have to get the two level scheduler to work.
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Implementing the 2lvl scehduler has it has been originally coded.
LRR on both the inner and outer levels
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Adding in a debug tracing system to GPGPU-Sim.
I am sick of writing debug code - then having to comment out, ifdef out or delete it to checkin.
This also allows for print streams so the user can decided which traces they would like to see.
Every print in GPGPU-Sim should go through this system - then it will be really easy to only get the information you want and more importantly people will (a) write and (b) checkin code that actually profiles what they are building.
Reading tracefiles is superiour in many ways to single stepping since you can print the world and just vet the logfile for what you need.
This also fascilitates advice from the Debugging Rules! book which states that you should never throw away a debugging tool. Having debug prints that don't get thrown away is big.
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Allowing the trace to be specified in the Make.
Run Make TRACE=0 to compile the code without any traces
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Allowing prints from the performance sim to get the actual ptx instruction text
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Getting the two level scheduler to actaully work...
What is released in fermi does not work at all - it effectively performs "static warp limit" from my CCWS paper.
Warps are never demoted from the active list since the functionality checking to see if they are waiting on a longop is completly broken.
Maybe if the original author had access to the tracing functions this would not have happened.
The islongop test was completely broken. It did not mark the register as used, it marked the register number in the instruction as used.
For example if this instruction was creating a long op:
ld r6 [r1]
It would mark register 0 as waiting for a long op (since it is register 0 of the two registers in this instruction), not register 6.
Additionally, whenever ANY instruction from a warp releases registers, ALL the longops being tracked for this warp get cleared....
The only way anyone ever thought this worked is if they did not test it....
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Reworking the warp schedulers to share common code.
Making the GTX480 use gto by default. I am not sure wht they really use, but it really can't be LRR.
Also adding in a new file for custom shared trace defines. These are useful when you want a print that has some
additional criteria or information printed.
Verified that the schedulers all work to a first order based on traces.
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Making it so you can run the stats collection scripts from any directory.
Also allow the caller to specify a stats file instead of just assume its always the same one
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15296]
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//depot/gpgpu_sim_research/fermi_locality/...
to //depot/gpgpu_sim_research/fermi/...
Adding in some protected constructors to the core cache classes.
This allows us to customize caches (for example having them use a custom tag array) more easily.
Also I made the in-class tag_array object in the baseline_cache into a pointer. This allows derived classes to easily create custom tag arrays.
I think in general, class extendibility is increased when pointers are used instead of in-object storage.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15223]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15218]
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Also fixing some really scary code that was memsetting the "*this" to 0.
The code sort of worked since there was only one member on the derived class (that was never referenced) and it
had no virtual functions. What I did to fix this is equally ugly, but far less dangerous.
I get a pointer to the start of the "plain old data (pod)" section of the class then memset it to 0.
Now the derived stats class can have more stuff on it than pod and we don't have to worry about stomping.
The "right" fix here is to not derive from pod and just make it a member with an accessor.
However, this is going to require all the client code to be re-written.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15203]
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[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 15198]
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