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path: root/src/gpgpu-sim
AgeCommit message (Expand)Author
2014-08-14Making the default L2 something saneTim Rogers
2014-08-14 - Fixing L1 Texture cache option (I updated the description to look like the...Ali Bakhoda
2014-08-14Actually fixing the atomic bugTim Rogers
2014-08-14Fixing the atomics I broke with the insn count fixTim Rogers
2014-08-14Fixing the varying instruction count when the cache configuration changes.Tim Rogers
2014-08-14Adding a print guard if there is no cacheTim Rogers
2014-08-14Integration change. - CL 9058 , adding the l1 cache stat print to the end of ...Tim Rogers
2014-08-14Integration change. CL 8980 - l1 cache stat printTim Rogers
2014-08-14Ejection from the interface buffer between interconnet and L2 happens in L2 c...Ali Bakhoda
2014-08-14Integrated in CL10323 from tm-test branchInderpreet Singh
2014-08-14Fix for Bug 111, integrated in CL10260Inderpreet Singh
2014-08-14Fix for Bug 110 - integrates in CL 10258 from tm-test branchInderpreet Singh
2014-08-14Added read to precharge constraint - negligible effect to DRAM efficiency.Inderpreet Singh
2014-08-14Fixed the DRAM timing model to add the write-read turn and write-precharge de...Wilson Fung
2014-08-14Integration change from CL8943 to fix barrier behaviour.Wilson Fung
2014-08-14fixup some dangling referencesTor Aamodt
2014-08-14change copyright notice to include authorsTor Aamodt
2014-08-14Fixing comment clobber from yesterdayTim Rogers
2011-07-07Integration change. Bringing in some changes from mem_divergence that allow f...Tim Rogers
2011-06-29changing copyright to BSDTor Aamodt
2011-05-28fix for bug 103Tor Aamodt
2011-05-26Another local memory address translation bug fix - it now adds an offset to p...Inderpreet Singh
2011-05-25Bug fix for local memory address translation that was made in tm-test branch ...Inderpreet Singh
2011-05-25Fix bug #100: local memory address translation returns multiple addressesInderpreet Singh
2011-03-03refactor pipeline stage namesTor Aamodt
2011-02-01Added configurable schedulers!aturner
2011-01-24Adds highly configurable opperand collectoraturner
2011-01-20Integration change. Bug fixes from AMD-CMU trace gen branch. Wilson Fung
2011-01-02integrateTor Aamodt
2011-01-02integrate bug fix (passes fast regression)Tor Aamodt
2010-12-28- parameter memory and active threads now part of kernel_info_t:Tor Aamodt
2010-12-28- Checkpointing new support for concurrent kernel execution (CUDA only, not O...Tor Aamodt
2010-11-30integrate changes (makes code more modular, i would argue)Tor Aamodt
2010-11-29make an explicit read operands stageTor Aamodt
2010-11-29integrate mask changesTor Aamodt
2010-11-28bug fix for ptxplus w/ data cache disabledTor Aamodt
2010-11-28enabling L2 data cache... it is write through, write evict like L1.Tor Aamodt
2010-11-28adding 1st level data cacheTor Aamodt
2010-10-240.9756 correlation. Set L1T line size to 128 bytes... problem wasTor Aamodt
2010-10-241. updates to .gdbinit fileTor Aamodt
2010-10-241. fix load imbalance issue (CTA's were filling up first core in a cluster be...Tor Aamodt
2010-10-24add back per shader icount tracking for visualizerTor Aamodt
2010-10-241. adding top level configuration class and making shader and memory configur...Tor Aamodt
2010-10-22enables global loads/stores for ptxplusTor Aamodt
2010-10-211. rewriting memory access generation code (from scratch), why not...Tor Aamodt
2010-10-19adding texture cache model with fragment fifo for latency hidingTor Aamodt
2010-10-18update lru state on hitTor Aamodt
2010-10-18Re-designed cache model:Tor Aamodt
2010-10-161. creating cache_config object to encapsulate cache configuration informationTor Aamodt
2010-10-161. refactoring histogram/logger so that classes are in header filesTor Aamodt
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