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2018-03-26Merge branch 'dev-purdue-integration' into dev-purdue-integrationTimothy G Rogers
2018-03-26Fixing resources limitation assertion for compute cab 61Mahmoud
2018-03-25Need to make sure we don't kill the L1 tootgrogers
2018-03-25Fixing a bug in mengchi's committgrogers
2018-03-25Add lonestar tick supportMengchi Zhang
Signed-off-by: Mengchi Zhang <[email protected]>
2018-03-12fixibg sectir l1 deadlock bugMahmoud
2017-11-19Doing lazy fetch-on-read policyMahmoud
2017-11-18Also initiate our L2 accesses on copies back to the CPUtgrogers
2017-11-18removing another asserttgrogers
2017-11-18Getting rid of another assert that crops up cause of our memcpy and L2 ↵tgrogers
interaction
2017-11-18copy to the L2 by defaulttgrogers
2017-11-18fixing the cycle issues with using the cudamemcpiestgrogers
2017-11-18Adding a subpartion trace to help in figuring out what the hell is going ontgrogers
2017-11-1864-address used on the CPU side, but GPGPU-Sim Truncates it to 32-bit.... ↵tgrogers
truncating the address here fixes the issue and we start propoerly hitting in the L2
2017-11-18fixing a stupid inheritance bugtgrogers
2017-11-18Making the perf sim copy optional, getting rid of an assert that will happen ↵tgrogers
with the new hack and incrementing the cycle so that cudamemcopies take some time (if we don't do this the LRU in the cache does not work)
2017-11-18vectoradd is successfully filling the l2tgrogers
2017-11-08Fixing the break limit bugMahmoud
2017-10-30adding new stats and change the PascalP100-HBM configMahmoud
2017-10-27add more statistics and chaging Pascal configMahmoud
2017-10-26fixing a typo in config fileMahmoud
2017-10-26Changing the Titan X config file to use the last modificationsMahmoud
2017-10-25The commits includes:Mahmoud
1- REEAD/WERITE buffer for DRAM 2- Fixing FETCH_ON_WRITE cahce policy bug
2017-10-13ensure that first launch uses simt cluster 0Mahmoud
2017-10-12remove Tex cache assertion and prevent spunit to execute DP instsMahmoud
2017-10-11Merge branch 'dev-purdue-integration' of ↵Mahmoud
https://github.rcac.purdue.edu/abdallm/gpgpu-sim_distribution into dev-purdue-integration
2017-10-11Sector Cache - first commitMahmoud
2017-10-11Fixing deadlock because of dp_unit (2)Mahmoud Khairy A. Abdallah
2017-10-11Fixing deadlock because of dp_unitMahmoud Khairy A. Abdallah
2017-09-14adding some condig commentsMahmoud
2017-09-14changing the DRAM bank indexing policyMahmoud
2017-09-14adding seperate sfu latency and init variablesMahmoud
2017-09-13Adding sperate dp_unitMahmoud
2017-09-13Fixing some typosMahmoud
2017-09-12Adding HBM modelMahmoud
2017-07-19Merge pull request #4 from abdallm/dev-purdue-integrationTimothy G Rogers
Interconnection assertion failing demystifying
2017-07-19Updaing the interconnect simulator to properly check for dependenciestgrogers
2017-07-19Adding some interconnection tracesMahmoud
2017-07-18Interconnection assertion failing demysstifyingMahmoud
2017-07-18Free buffer interconnection assertionMahmoud
2017-07-18Fixing deadlock bugMahmoud
2017-07-17Fixing some typos and adding commentsMahmoud
2017-07-17Improving GPU core model. This commits contains:Mahmoud
1- round robin inst issue for warp multiple schedulers 2- add sector mask in the memory request (to bused later for L2 sector cache) 3- Adding Fermi coalescer 4- Ensure different exen units are used in dual_issue mode 5- Report how many dual_issue happened 6- Adding oldest_first scheduler
2017-07-12Fixing BankGroup Indexing BugMahmoud
2017-07-06Adding the correct dependency for the detailed_version file. In order to ↵tgrogers
updatet the built number output when we run gpgpu-sim we need to recompile cuda-sim everytime the detailed_version has changed
2017-05-17Changing the version detection to be much more detailed. Now the git commit ↵tgrogers
# and branch will be embedded in the built executable and print out when gpgpu-sim runs
2017-05-09Fix next block addr to link predicate ret block to consecutive blockMengchi Zhang
The block containing predicate ret instruction should add the consecutive block to its successor_ids set. next_addr should be assigned with current instruction address add instruction size instead of 1. Signed-off-by: Mengchi Zhang <[email protected]>
2016-09-06Merge pull request #30 from sspenst/devgpgpu-sim
shfl instruction implemented
2016-09-05Merge pull request #28 from jwang323/cdp_cleangpgpu-sim
Initial support of CUDA Dynamic Parallelism on GPGPUSim
2016-09-05MOD: modify Makefile to make CUDART_VERSION available to gpu-sim.ccJin Wang
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