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AgeCommit message (Expand)Author
2011-05-25Bug fix for local memory address translation that was made in tm-test branch ...Inderpreet Singh
2011-05-25Fix bug #100: local memory address translation returns multiple addressesInderpreet Singh
2011-03-03refactor pipeline stage namesTor Aamodt
2011-02-01Added configurable schedulers!aturner
2011-01-24Adds highly configurable opperand collectoraturner
2011-01-20Integration change. Bug fixes from AMD-CMU trace gen branch. Wilson Fung
2011-01-02integrateTor Aamodt
2011-01-02integrate bug fix (passes fast regression)Tor Aamodt
2010-12-28the assertionTor Aamodt
2010-12-28- parameter memory and active threads now part of kernel_info_t:Tor Aamodt
2010-12-28- Checkpointing new support for concurrent kernel execution (CUDA only, not O...Tor Aamodt
2010-12-21added support for negative .f64 operands in decuda_to_ptxplusJimmy Kwa
2010-12-20fix from CL 8285Tor Aamodt
2010-12-15Added next instruction type to ptxplus, ".ff64". It's the same as ".f64" exce...Jimmy Kwa
2010-11-30integrate changes (makes code more modular, i would argue)Tor Aamodt
2010-11-29make an explicit read operands stageTor Aamodt
2010-11-29integrate mask changesTor Aamodt
2010-11-28bug fix for ptxplus w/ data cache disabledTor Aamodt
2010-11-28enabling L2 data cache... it is write through, write evict like L1.Tor Aamodt
2010-11-28adding 1st level data cacheTor Aamodt
2010-11-15Cleaned up decuda_to_ptxplus code to remove compiler warningsJimmy Kwa
2010-10-240.9756 correlation. Set L1T line size to 128 bytes... problem wasTor Aamodt
2010-10-241. updates to .gdbinit fileTor Aamodt
2010-10-241. fix load imbalance issue (CTA's were filling up first core in a cluster be...Tor Aamodt
2010-10-24add back per shader icount tracking for visualizerTor Aamodt
2010-10-241. adding top level configuration class and making shader and memory configur...Tor Aamodt
2010-10-22enables global loads/stores for ptxplusTor Aamodt
2010-10-211. rewriting memory access generation code (from scratch), why not...Tor Aamodt
2010-10-19adding texture cache model with fragment fifo for latency hidingTor Aamodt
2010-10-18update lru state on hitTor Aamodt
2010-10-18Re-designed cache model:Tor Aamodt
2010-10-161. creating cache_config object to encapsulate cache configuration informationTor Aamodt
2010-10-161. refactoring histogram/logger so that classes are in header filesTor Aamodt
2010-10-161. moving address decoding into a class (and out of cache entirely)Tor Aamodt
2010-10-121. adding simt_core_cluster, which models a TPC or (for fermi) GPC...Tor Aamodt
2010-10-101. create function unit classes for SP, SFU, LD/ST.Tor Aamodt
2010-10-09refactor: renaming some texture reference variables after moving to gpgpu_tTor Aamodt
2010-10-09refactoring: moving texture reference mappings into gpgpu_t Tor Aamodt
2010-10-09Refactoring:Tor Aamodt
2010-10-081. modify shader_core_ctx::execute_pipe() to model instruction throughput cor...Tor Aamodt
2010-10-08some fixes for ptxplus (correlation test now running)Tor Aamodt
2010-10-081. refactoring cuda api code for loading PTX (removing external PTX loading e...Tor Aamodt
2010-10-05simulator "working" on ptxplus, simulated IPC "too low" by about a factor of ...Tor Aamodt
2010-10-05bug fixesTor Aamodt
2010-10-05broken change list: builds, but does not run, yetTor Aamodt
2010-10-03bug fix for last check in (problem w/ CUDA 3.1 regressions)Tor Aamodt
2010-10-03moving some CUDA API centric code to cuda_runtime_api.ccTor Aamodt
2010-10-031. integrating Inder's changesTor Aamodt
2010-10-031. enable L2 cache as a texture cache (also some bug fixes for L2 as regular ...Tor Aamodt
2010-10-02refactor: mem_fetch now a classTor Aamodt
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