| Age | Commit message (Expand) | Author |
|---|
| 2014-08-14 | Undoing the rest of files mistakly changed in CL10695, this change completes ... | Ayub Gubran |
| 2014-08-14 | Adding a print guard if there is no cache | Tim Rogers |
| 2014-08-14 | Integration change. - CL 9058 , adding the l1 cache stat print to the end of ... | Tim Rogers |
| 2014-08-14 | Integration change. CL 8980 - l1 cache stat print | Tim Rogers |
| 2014-08-14 | Undoing a change that should't be in this branch. | Ayub Gubran |
| 2014-08-14 | My last work added to the branch, wokring on the functional simulator in cuda... | Ayub Gubran |
| 2014-08-14 | Integrated 9556: | Andrew M. B. Boktor |
| 2014-08-14 | Build fix, | Andrew M. B. Boktor |
| 2014-08-14 | Ejection from the interface buffer between interconnet and L2 happens in L2 c... | Ali Bakhoda |
| 2014-08-14 | - Minor change to make things simpler, basically removing all instances of | Andrew M. B. Boktor |
| 2014-08-14 | Integrated in CL10323 from tm-test branch | Inderpreet Singh |
| 2014-08-14 | Fix for Bug 111, integrated in CL10260 | Inderpreet Singh |
| 2014-08-14 | Fix for Bug 110 - integrates in CL 10258 from tm-test branch | Inderpreet Singh |
| 2014-08-14 | Fix for Bug 109 - memory alignment should be 256 bytes. | Inderpreet Singh |
| 2014-08-14 | Assigned debug level 3 to stream manager output. | Inderpreet Singh |
| 2014-08-14 | Added read to precharge constraint - negligible effect to DRAM efficiency. | Inderpreet Singh |
| 2014-08-14 | release!?! | Tor Aamodt |
| 2014-08-14 | Fixed the DRAM timing model to add the write-read turn and write-precharge de... | Wilson Fung |
| 2014-08-14 | ready to release? | Tor Aamodt |
| 2014-08-14 | Fixes for atomic callbacks | arun |
| 2014-08-14 | Integration change from CL8943 to fix barrier behaviour. | Wilson Fung |
| 2014-08-14 | fixup some dangling references | Tor Aamodt |
| 2014-08-14 | change copyright notice to include authors | Tor Aamodt |
| 2014-08-14 | Fixing comment clobber from yesterday | Tim Rogers |
| 2011-07-07 | Integration change. Bringing in some changes from mem_divergence that allow f... | Tim Rogers |
| 2011-06-30 | version info | Tor Aamodt |
| 2011-06-29 | changing copyright to BSD | Tor Aamodt |
| 2011-06-29 | Adding back stat for memory divergence | Tim Rogers |
| 2011-05-28 | fix for bug 103 | Tor Aamodt |
| 2011-05-26 | Another local memory address translation bug fix - it now adds an offset to p... | Inderpreet Singh |
| 2011-05-25 | Bug fix for local memory address translation that was made in tm-test branch ... | Inderpreet Singh |
| 2011-05-25 | Fix bug #100: local memory address translation returns multiple addresses | Inderpreet Singh |
| 2011-03-03 | refactor pipeline stage names | Tor Aamodt |
| 2011-02-01 | Added configurable schedulers! | aturner |
| 2011-01-24 | Adds highly configurable opperand collector | aturner |
| 2011-01-20 | Integration change. Bug fixes from AMD-CMU trace gen branch. | Wilson Fung |
| 2011-01-02 | integrate | Tor Aamodt |
| 2011-01-02 | integrate bug fix (passes fast regression) | Tor Aamodt |
| 2010-12-28 | the assertion | Tor Aamodt |
| 2010-12-28 | - parameter memory and active threads now part of kernel_info_t: | Tor Aamodt |
| 2010-12-28 | - Checkpointing new support for concurrent kernel execution (CUDA only, not O... | Tor Aamodt |
| 2010-12-21 | added support for negative .f64 operands in decuda_to_ptxplus | Jimmy Kwa |
| 2010-12-20 | fix from CL 8285 | Tor Aamodt |
| 2010-12-15 | Added next instruction type to ptxplus, ".ff64". It's the same as ".f64" exce... | Jimmy Kwa |
| 2010-11-30 | integrate changes (makes code more modular, i would argue) | Tor Aamodt |
| 2010-11-29 | make an explicit read operands stage | Tor Aamodt |
| 2010-11-29 | integrate mask changes | Tor Aamodt |
| 2010-11-28 | bug fix for ptxplus w/ data cache disabled | Tor Aamodt |
| 2010-11-28 | enabling L2 data cache... it is write through, write evict like L1. | Tor Aamodt |
| 2010-11-28 | adding 1st level data cache | Tor Aamodt |
