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# functional simulator specification
-gpgpu_ptx_instruction_classification 0
-gpgpu_ptx_sim_mode 0
-gpgpu_ptx_force_max_capability 13
# high level architecture configuration
-gpgpu_n_clusters 10
-gpgpu_n_cores_per_cluster 3
-gpgpu_n_mem 8
-gpgpu_clock_domains 325.0:650.0:650.0:800.0
# shader core pipeline config
-gpgpu_shader_registers 16384
-gpgpu_shader_core_pipeline 1024:32
-gpgpu_shader_cta 8
-gpgpu_simd_model 1
# Pipeline widths and number of FUs
# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
-gpgpu_pipeline_widths 1,1,1,1,1,1,1
-gpgpu_num_sp_units 1
-gpgpu_num_sfu_units 1
# Instruction latencies and initiation intervals
# "ADD,MAX,MUL,MAD,DIV"
-ptx_opcode_latency_int 1,1,19,25,145
-ptx_opcode_initiation_int 1,1,4,4,32
-ptx_opcode_latency_fp 1,1,1,1,30
-ptx_opcode_initiation_fp 1,1,1,1,5
-ptx_opcode_latency_dp 8,8,8,8,335
-ptx_opcode_initiation_dp 8,8,8,8,130
# memory stage behaviour
# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
-gpgpu_cache:il1 4:256:4,L:R:f:N:L,A:2:32,4
-gpgpu_tex_cache:l1 8:128:5,L:R:m:N:L,F:128:4,128:2
-gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
-gpgpu_cache:dl2 16:256:8,L:B:m:W:L,A:16:4,4
-gpgpu_cache:dl2_texture_only 1
-gpgpu_shmem_warp_parts 2
# interconnection
-network_mode 1
-inter_config_file config_quadro_islip.icnt
# dram scheduler config
-gpgpu_dram_scheduler 1
# The DRAM return queue and the scheduler queue together should provide buffer
# to sustain the memory level parallelism to tolerate DRAM latency
# To allow 100% DRAM utility, there should at least be enough buffer to sustain
# the minimum DRAM latency (30 core cycles). I.e.
# Total buffer space required = 30 x 800MHz / 325MHz = 74
-gpgpu_frfcfs_dram_sched_queue_size 16
-gpgpu_dram_return_queue_size 58
# dram model config
-gpgpu_n_mem_per_ctrlr 2
-gpgpu_dram_buswidth 4
-gpgpu_dram_burst_length 4
-dram_data_command_freq_ratio 2 # GDDR3 is DDR
-gpgpu_mem_address_mask 1
-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS
# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz
-gpgpu_dram_timing_opt nbk=8:CCD=2:RRD=8:RCD=12:RAS=25:RP=10:RC=35:CL=10:WL=7:CDLR=6:WR=11
# stat collection
-gpgpu_memlatency_stat 14
-gpgpu_runtime_stat 500
-enable_ptx_file_line_stats 1
# SASS execution (only supported with CUDA >= 4.0)
-gpgpu_ptx_convert_to_ptxplus 0
-gpgpu_ptx_save_converted_ptxplus 0
# enable operand collector
-gpgpu_operand_collector_num_units_sp 6
-gpgpu_operand_collector_num_units_sfu 8
-visualizer_enabled 0
# tracing functionality
#-trace_enabled 1
#-trace_components WARP_SCHEDULER,SCOREBOARD
#-trace_sampling_core 0
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