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# functional simulator specification
-gpgpu_ptx_instruction_classification 0
-gpgpu_ptx_sim_mode 0
-gpgpu_ptx_force_max_capability 12
# high level architecture configuration
-gpgpu_n_clusters 10
-gpgpu_n_cores_per_cluster 3
-gpgpu_n_mem 8
-gpgpu_clock_domains 325.0:650.0:650.0:800.0
# shader core pipeline config
-gpgpu_shader_registers 16384
-gpgpu_shader_core_pipeline 1024:32
-gpgpu_shader_cta 8
-gpgpu_simd_model 1
# memory stage behaviour
-gpgpu_cache:il1 4:256:4:L:R:f,A:2:32,4
-gpgpu_tex_cache:l1 8:128:5:L:R:m,F:128:4,128:2
-gpgpu_const_cache:l1 64:64:2:L:R:f,A:2:32,4
-gpgpu_cache:dl2 16:256:8:L:R:m,A:16:4,4
-gpgpu_cache:dl2_texture_only 1
-gpgpu_shmem_warp_parts 2
# interconnection
-network_mode 1
-inter_config_file icnt_config_quadro_islip.txt
# dram model config
-gpgpu_dram_scheduler 1
-gpgpu_dram_sched_queue_size 16
-gpgpu_n_mem_per_ctrlr 2
-gpgpu_dram_buswidth 4
-gpgpu_dram_burst_length 4
-gpgpu_mem_address_mask 1
-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RRBBBCCC.CCCSSSSS
# GDDR3 timing from Samsung K4J52324QH-HC12 @ 800MHz
# {nbk:nbkgrp:tCCD:tCCDL:tRRD:tRCD:tRAS:tRP:tRTPL:tRC:CL:WL:tCDLR:tWR}
-gpgpu_dram_timing_opt 8:1:2:0:8:12:25:10:0:35:10:7:6:11
# stat collection
-gpgpu_memlatency_stat 14
-gpgpu_runtime_stat 500
-enable_ptx_file_line_stats 1
# Using cuobjdump to extract ptx/SASS
-gpgpu_ptx_use_cuobjdump 0
# SASS execution (only supported with CUDA >= 4.0)
-gpgpu_ptx_convert_to_ptxplus 0
-gpgpu_ptx_save_converted_ptxplus 0
# enable operand collector
-gpgpu_operand_collector_num_units_sp 6
-gpgpu_operand_collector_num_units_sfu 8
-visualizer_enabled 0
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