1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
|
# This config models the Pascal GP102 (NVIDIA TITAN X)
# For more info about this card, see Nvidia White paper
# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf
# functional simulator specification
-gpgpu_ptx_instruction_classification 0
-gpgpu_ptx_sim_mode 0
-gpgpu_ptx_force_max_capability 61
-gpgpu_ignore_resources_limitation 1
# Device Limits
-gpgpu_stack_size_limit 1024
-gpgpu_heap_size_limit 8388608
-gpgpu_runtime_sync_depth_limit 2
-gpgpu_runtime_pending_launch_count_limit 2048
# Compute Capability
-gpgpu_compute_capability_major 6
-gpgpu_compute_capability_minor 1
# SASS execution (only supported with CUDA >= 4.0)
-gpgpu_ptx_convert_to_ptxplus 0
-gpgpu_ptx_save_converted_ptxplus 0
# high level architecture configuration
# P102 has two semi-indp scheds per core, and two cores per cluster
-gpgpu_n_clusters 28
-gpgpu_n_cores_per_cluster 2
-gpgpu_n_mem 12
-gpgpu_n_sub_partition_per_mchannel 2
# Pascal clock domains
#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
# Pascal NVIDIA TITAN X clock domains are adopted from
# https://en.wikipedia.org/wiki/GeForce_10_series
-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
# shader core pipeline config
-gpgpu_shader_registers 32768
-gpgpu_occupancy_sm_number 62
# This implies a maximum of 32 warps/SM
-gpgpu_shader_core_pipeline 1024:32
-gpgpu_shader_cta 16
-gpgpu_simd_model 1
# Pipeline widths and number of FUs
# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB
## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM. In this config, we split SM into two shader cores, each has 2 SPs and 2 SFUs
# There is no int unit in Pascal
## we need to scale the number of pipeline registers to be equal to the number of SP units
-gpgpu_pipeline_widths 2,1,0,2,1,2,1,0,2,1,5
-gpgpu_num_sp_units 2
-gpgpu_num_sfu_units 2
-gpgpu_num_dp_units 1
# Instruction latencies and initiation intervals
# "ADD,MAX,MUL,MAD,DIV"
# All Div operations are executed on SFU unit
# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
-ptx_opcode_latency_int 4,13,4,5,145
-ptx_opcode_initiation_int 1,1,1,1,4
-ptx_opcode_latency_fp 4,13,4,5,39
-ptx_opcode_initiation_fp 1,2,1,1,4
-ptx_opcode_latency_dp 8,19,8,8,330
-ptx_opcode_initiation_dp 8,8,8,8,130
-ptx_opcode_initiation_sfu 4
-ptx_opcode_latency_sfu 8
# latencies and cache configs are adopted from:
# https://arxiv.org/pdf/1804.06826.pdf
# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
# Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB
# Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache
# The defulat is to disable the L1 cache, unless cache modifieres are used
-gpgpu_cache:dl1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
-gpgpu_cache:dl1PrefL1 S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
-gpgpu_cache:dl1PrefShared S:4:128:48,L:L:s:N:L,A:256:8,16:0,32
-gpgpu_shmem_size 49152
-gpgpu_shmem_size_PrefL1 49152
-gpgpu_shmem_size_PrefShared 49152
# By default, L1 cache is disabled in Pascal P102.
# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1
-gmem_skip_L1D 1
-icnt_flit_size 40
-gpgpu_n_cluster_ejection_buffer_size 32
-l1_latency 82
-smem_latency 24
-gpgpu_flush_l1_cache 1
# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32
-gpgpu_cache:dl2_texture_only 0
-gpgpu_dram_partition_queues 32:32:32:32
-perf_sim_memcpy 1
-memory_partition_indexing 0
# 4 KB Inst.
-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
# 48 KB Tex
# Note, TEX is deprected in Pascal, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
# 12 KB Const
-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
# enable operand collector
-gpgpu_operand_collector_num_units_sp 12
-gpgpu_operand_collector_num_units_sfu 6
-gpgpu_operand_collector_num_units_mem 8
-gpgpu_operand_collector_num_units_dp 6
-gpgpu_operand_collector_num_in_ports_sp 2
-gpgpu_operand_collector_num_out_ports_sp 2
-gpgpu_operand_collector_num_in_ports_sfu 2
-gpgpu_operand_collector_num_out_ports_sfu 2
-gpgpu_operand_collector_num_in_ports_mem 1
-gpgpu_operand_collector_num_out_ports_mem 1
-gpgpu_operand_collector_num_in_ports_dp 1
-gpgpu_operand_collector_num_out_ports_dp 1
-gpgpu_num_reg_banks 32
# shared memory bankconflict detection
-gpgpu_shmem_num_banks 32
-gpgpu_shmem_limited_broadcast 0
-gpgpu_shmem_warp_parts 1
# Use Pascal Coalsce arhitetecture
-gpgpu_coalesce_arch 61
## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
-gpgpu_max_insn_issue_per_warp 2
-gpgpu_dual_issue_diff_exec_units 1
# interconnection
-network_mode 1
-inter_config_file config_fermi_islip.icnt
# memory partition latency config
-rop_latency 120
-dram_latency 100
# dram model config
-gpgpu_dram_scheduler 1
-gpgpu_frfcfs_dram_sched_queue_size 64
-gpgpu_dram_return_queue_size 64
# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
# the atom size of GDDR5X (the smallest read request) is 32 bytes
-gpgpu_n_mem_per_ctrlr 1
-gpgpu_dram_buswidth 4
-gpgpu_dram_burst_length 8
-dram_data_command_freq_ratio 4 # GDDR5X is QDR
-gpgpu_mem_address_mask 1
-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
# Use the same GDDR5 timing, scaled to 2500MHZ
-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52:
CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3"
-dram_bnk_indexing_policy 0
-dram_bnkgrp_indexing_policy 1
#-Seperate_Write_Queue_Enable 1
#-Write_Queue_Size 64:56:32
# Pascal 102 has four schedulers per core
-gpgpu_num_sched_per_core 2
# Two Level Scheduler with active and pending pools
#-gpgpu_scheduler two_level_active:6:0:1
# Loose round robbin scheduler
#-gpgpu_scheduler lrr
# Greedy then oldest scheduler
-gpgpu_scheduler gto
# stat collection
-gpgpu_memlatency_stat 14
-gpgpu_runtime_stat 500
-enable_ptx_file_line_stats 1
-visualizer_enabled 0
# power model configs, disable it untill we create a real energy model for Pascal 102
-power_simulation_enabled 0
# tracing functionality
#-trace_enabled 1
#-trace_components WARP_SCHEDULER,SCOREBOARD
#-trace_sampling_core 0
|
