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# Copyright (c) 2018-2021, Vijay Kandiah, Junrui Pan, Mahmoud Khairy, Scott Peverelle, Timothy Rogers, Tor M. Aamodt, Nikos Hardavellas
# Northwestern University, Purdue University, The University of British Columbia
# All rights reserved.
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# 1. Redistributions of source code must retain the above copyright notice, this
# list of conditions and the following disclaimer;
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution;
# 3. Neither the names of Northwestern University, Purdue University,
# The University of British Columbia nor the names of their contributors
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
# This config models the Pascal GP102 (NVIDIA TITAN X)
# For more info about this card, see Nvidia White paper
# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf
# functional simulator specification
-gpgpu_ptx_instruction_classification 0
-gpgpu_ptx_sim_mode 0
-gpgpu_ptx_force_max_capability 61
-gpgpu_ignore_resources_limitation 1
# Device Limits
-gpgpu_stack_size_limit 1024
-gpgpu_heap_size_limit 8388608
-gpgpu_runtime_sync_depth_limit 2
-gpgpu_runtime_pending_launch_count_limit 2048
-gpgpu_kernel_launch_latency 5000
# Compute Capability
-gpgpu_compute_capability_major 6
-gpgpu_compute_capability_minor 1
# SASS execution (only supported with CUDA >= 4.0)
-gpgpu_ptx_convert_to_ptxplus 0
-gpgpu_ptx_save_converted_ptxplus 0
# high level architecture configuration
-gpgpu_n_clusters 28
-gpgpu_n_cores_per_cluster 1
-gpgpu_n_mem 12
-gpgpu_n_sub_partition_per_mchannel 2
-gpgpu_clock_gated_lanes 1
# Pascal clock domains
#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
# Pascal NVIDIA TITAN X clock domains are adopted from
# https://en.wikipedia.org/wiki/GeForce_10_series
-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
# shader core pipeline config
-gpgpu_shader_registers 65536
-gpgpu_occupancy_sm_number 62
# This implies a maximum of 32 warps/SM
-gpgpu_shader_core_pipeline 2048:32
-gpgpu_shader_cta 32
-gpgpu_simd_model 1
# Pipeline widths and number of FUs
# ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB
## Pascal GP102 has 4 SP SIMD units and 4 SFU units per SM.
# There is no INT unit in Pascal
-gpgpu_pipeline_widths 4,0,0,4,4,4,0,0,4,4,8
-gpgpu_num_sp_units 4
-gpgpu_num_sfu_units 4
# Instruction latencies and initiation intervals
# "ADD,MAX,MUL,MAD,DIV,SHFL"
# All Div operations are executed on SFU unit
-ptx_opcode_latency_int 4,13,4,5,145,32
-ptx_opcode_initiation_int 1,1,1,1,4,4
-ptx_opcode_latency_fp 4,13,4,4,39
-ptx_opcode_initiation_fp 1,2,1,1,4
-ptx_opcode_latency_dp 8,19,8,8,330
-ptx_opcode_initiation_dp 8,8,8,8,130
-ptx_opcode_initiation_sfu 4
-ptx_opcode_latency_sfu 20
# in sub_core_model, schedulers are isolated, each scheduler has its own register file and EUs
-gpgpu_sub_core_model 1
# enable operand collector
# disable specialized operand collectors and use generic operand collectors instead
-gpgpu_enable_specialized_operand_collector 0
-gpgpu_operand_collector_num_units_gen 8
-gpgpu_operand_collector_num_in_ports_gen 8
-gpgpu_operand_collector_num_out_ports_gen 8
# 16 register banks, 4 banks per subcore
-gpgpu_num_reg_banks 16
-gpgpu_reg_file_port_throughput 2
# shared memory bankconflict detection
-gpgpu_shmem_num_banks 32
-gpgpu_shmem_limited_broadcast 0
-gpgpu_shmem_warp_parts 1
# Use Pascal Coalsce arhitetecture
-gpgpu_coalesce_arch 61
# Pascal 102 has four schedulers per core
-gpgpu_num_sched_per_core 4
# Greedy then oldest scheduler
-gpgpu_scheduler gto
## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
-gpgpu_max_insn_issue_per_warp 2
-gpgpu_dual_issue_diff_exec_units 1
## L1/shared memory configuration
# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
# ** Optional parameter - Required when mshr_type==Texture Fifo
# Note: Hashing set index function (H) only applies to a set size of 32 or 64.
# The defulat is to disable the L1 cache, unless cache modifieres are used
-gpgpu_l1_banks 2
-gpgpu_cache:dl1 S:4:128:96,L:L:s:N:L,A:256:8,16:0,32
-gpgpu_cache:dl1PrefL1 S:4:128:96,L:L:s:N:L,A:256:8,16:0,32
-gpgpu_cache:dl1PrefShared S:4:128:96,L:L:s:N:L,A:256:8,16:0,32
-gpgpu_shmem_size 98304
-gpgpu_shmem_sizeDefault 98304
-gpgpu_shmem_size_PrefL1 98304
-gpgpu_shmem_size_PrefShared 98304
# By default, L1 cache is disabled in Pascal P102.
# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1
-gpgpu_gmem_skip_L1D 1
-icnt_flit_size 40
-gpgpu_n_cluster_ejection_buffer_size 32
-gpgpu_l1_latency 82
-gpgpu_smem_latency 24
-gpgpu_flush_l1_cache 1
# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:P,A:256:64,16:0,32
-gpgpu_cache:dl2_texture_only 0
-gpgpu_dram_partition_queues 32:32:32:32
-gpgpu_perf_sim_memcpy 1
-gpgpu_memory_partition_indexing 4
# 4 KB Inst.
-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
-gpgpu_inst_fetch_throughput 8
# 48 KB Tex
# Note, TEX is deprected in Pascal, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
# 12 KB Const
-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
-gpgpu_perfect_inst_const_cache 1
# interconnection
-network_mode 1
-inter_config_file config_pascal_islip.icnt
# memory partition latency config
-gpgpu_l2_rop_latency 120
-dram_latency 100
# dram model config
-gpgpu_dram_scheduler 1
-gpgpu_frfcfs_dram_sched_queue_size 64
-gpgpu_dram_return_queue_size 64
# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
# the atom size of GDDR5X (the smallest read request) is 32 bytes
-gpgpu_n_mem_per_ctrlr 1
-gpgpu_dram_buswidth 4
-gpgpu_dram_burst_length 8
-dram_data_command_freq_ratio 4 # GDDR5X is QDR
-gpgpu_mem_address_mask 1
-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
# Use the same GDDR5 timing, scaled to 2500MHZ
-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52:
CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3"
-dram_bnk_indexing_policy 0
-dram_bnkgrp_indexing_policy 1
#-dram_seperate_write_queue_enable 1
#-dram_write_queue_size 64:56:32
# stat collection
-gpgpu_memlatency_stat 14
-gpgpu_runtime_stat 500
-enable_ptx_file_line_stats 1
-visualizer_enabled 0
# tracing functionality
#-trace_enabled 1
#-trace_components WARP_SCHEDULER,SCOREBOARD
#-trace_sampling_core 0
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