1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
|
// Copyright (c) 2009-2011, Tor M. Aamodt
// The University of British Columbia
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
// Redistributions in binary form must reproduce the above copyright notice, this
// list of conditions and the following disclaimer in the documentation and/or
// other materials provided with the distribution.
// Neither the name of The University of British Columbia nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#ifndef MC_PARTITION_INCLUDED
#define MC_PARTITION_INCLUDED
#include "dram.h"
#include "../abstract_hardware_model.h"
#include <list>
#include <queue>
class mem_fetch;
class partition_mf_allocator : public mem_fetch_allocator {
public:
partition_mf_allocator( const memory_config *config )
{
m_memory_config = config;
}
virtual mem_fetch * alloc(const class warp_inst_t &inst, const mem_access_t &access) const
{
abort();
return NULL;
}
virtual mem_fetch * alloc(new_addr_type addr, mem_access_type type, unsigned size, bool wr) const;
private:
const memory_config *m_memory_config;
};
class memory_partition_unit
{
public:
memory_partition_unit( unsigned partition_id, const struct memory_config *config, class memory_stats_t *stats );
~memory_partition_unit();
bool busy() const;
void cache_cycle( unsigned cycle );
void dram_cycle();
bool full() const;
void push( class mem_fetch* mf, unsigned long long clock_cycle );
class mem_fetch* pop();
class mem_fetch* top();
void set_done( mem_fetch *mf );
unsigned flushL2();
void visualizer_print( gzFile visualizer_file );
void print_cache_stat(unsigned &accesses, unsigned &misses) const;
void print_stat( FILE *fp ) { m_dram->print_stat(fp); }
void visualize() const { m_dram->visualize(); }
void print( FILE *fp ) const;
private:
// data
unsigned m_id;
const struct memory_config *m_config;
class dram_t *m_dram;
class l2_cache *m_L2cache;
class L2interface *m_L2interface;
partition_mf_allocator *m_mf_allocator;
// model delay of ROP units with a fixed latency
struct rop_delay_t
{
unsigned long long ready_cycle;
class mem_fetch* req;
};
std::queue<rop_delay_t> m_rop;
// model DRAM access scheduler latency (fixed latency between L2 and DRAM)
struct dram_delay_t
{
unsigned long long ready_cycle;
class mem_fetch* req;
};
std::queue<dram_delay_t> m_dram_latency_queue;
// these are various FIFOs between units within a memory partition
fifo_pipeline<mem_fetch> *m_icnt_L2_queue;
fifo_pipeline<mem_fetch> *m_L2_dram_queue;
fifo_pipeline<mem_fetch> *m_dram_L2_queue;
fifo_pipeline<mem_fetch> *m_L2_icnt_queue; // L2 cache hit response queue
class mem_fetch *L2dramout;
unsigned long long int wb_addr;
class memory_stats_t *m_stats;
std::set<mem_fetch*> m_request_tracker;
friend class L2interface;
};
class L2interface : public mem_fetch_interface {
public:
L2interface( memory_partition_unit *unit ) { m_unit=unit; }
virtual bool full( unsigned size, bool write) const
{
// assume read and write packets all same size
return m_unit->m_L2_dram_queue->full();
}
virtual void push(mem_fetch *mf)
{
mf->set_status(IN_PARTITION_L2_TO_DRAM_QUEUE,0/*FIXME*/);
m_unit->m_L2_dram_queue->push(mf);
}
private:
memory_partition_unit *m_unit;
};
#endif
|
