Final pass on power model reformat (comments...)

4 files changed, 37 insertions, 28 deletions

diff --git a/src/gpuwattch/array.cc b/src/gpuwattch/array.cc
index 6cb2f3b..eea1e67 100644
--- a/src/gpuwattch/array.cc
+++ b/src/gpuwattch/array.cc
@@ -174,21 +174,21 @@ void ArrayST::optimize_array() {
     //				CAM structures can be heavily pipelined and use
     // look-ahead techniques, 				therefore timing can be
     // relaxed. But McPAT does not model the
-    // advanced 				techniques. If continue optimizing, the area efficiency
-    // will be too low
+    // advanced 				techniques. If continue optimizing, the
+    // area efficiency will be too low
     //		*/
     //		//For CAM and FA, stop opt if area efficiency is too low
     //		if (throughput_overflow==true)
     //			cout<< "Warning: " <<" McPAT stopped optimization on
-    //throughput for
+    // throughput for
     //"<< name
     //				<<" array structure because its area efficiency
-    //is below
+    // is below
     //"<<area_efficiency_threshold<<"% " << endl; 		if
-    //(latency_overflow==true) 			cout<< "Warning: " <<" McPAT stopped
-    //optimization on latency for "<< name
+    //(latency_overflow==true) 			cout<< "Warning: " <<" McPAT
+    // stopped optimization on latency for "<< name
     //				<<" array structure because its area efficiency
-    //is below
+    // is below
     //"<<area_efficiency_threshold<<"% " << endl;
     //	}
 
diff --git a/src/gpuwattch/core.cc b/src/gpuwattch/core.cc
index f2376fe..77a5565 100644
--- a/src/gpuwattch/core.cc
+++ b/src/gpuwattch/core.cc
@@ -804,7 +804,7 @@ SchedulerU::SchedulerU(ParseXML* XML_interface, int ithCore_,
         // can know which reg/RRAT to update
         //				data =
         // int(ceil((robExtra+coredynp.pc_width
-        //+ 						coredynp.instruction_length
+        //+ coredynp.instruction_length
         //+ 2*coredynp.phy_ireg_width)/8.0));
         data = int(ceil(
             (robExtra + coredynp.pc_width + coredynp.phy_ireg_width) / 8.0));
@@ -812,7 +812,7 @@ SchedulerU::SchedulerU(ParseXML* XML_interface, int ithCore_,
         // in RS based OOO, ROB also contains value of destination reg
         //				data  =
         // int(ceil((robExtra+coredynp.pc_width
-        //+ 						coredynp.instruction_length
+        //+ coredynp.instruction_length
         //+ 2*coredynp.phy_ireg_width + coredynp.fp_data_width)/8.0));
         data = int(ceil((robExtra + coredynp.pc_width +
                          coredynp.phy_ireg_width + coredynp.fp_data_width) /
@@ -2400,18 +2400,19 @@ RENAMINGU::RENAMINGU(ParseXML* XML_interface, int ithCore_,
         // int(ceil(coredynp.phy_ireg_width/8.0)*coredynp.num_IRF_entry);
         // out_w = data; 			interface_ip.is_cache
         //= false; 			interface_ip.pure_cam            =
-        //false; 			interface_ip.pure_ram            = true; 			interface_ip.line_sz
-        //= data; 			interface_ip.cache_sz            =
-        // data*coredynp.globalCheckpoint; interface_ip.assoc = 1;
+        // false; 			interface_ip.pure_ram            = true;
+        // interface_ip.line_sz = data; 			interface_ip.cache_sz
+        // = data*coredynp.globalCheckpoint; interface_ip.assoc = 1;
         // interface_ip.nbanks              = 1;
         // interface_ip.out_w =
         // out_w*8; 			interface_ip.access_mode         = 0;
         // interface_ip.throughput = 1.0/clockRate;
-        //interface_ip.latency = 1.0/clockRate; 			interface_ip.obj_func_dyn_energy
-        //= 0; 			interface_ip.obj_func_dyn_power  = 0;
-        //			interface_ip.obj_func_leak_power = 0;
-        //			interface_ip.obj_func_cycle_t    = 1;
-        //			interface_ip.num_rw_ports    = 1;//the extra one
+        // interface_ip.latency = 1.0/clockRate;
+        // interface_ip.obj_func_dyn_energy = 0;
+        // interface_ip.obj_func_dyn_power  = 0;
+        // interface_ip.obj_func_leak_power = 0;
+        //interface_ip.obj_func_cycle_t    = 1;
+        //interface_ip.num_rw_ports = 1;//the extra one
         // port is for GCs 			interface_ip.num_rd_ports    =
         // 2*coredynp.decodeW; 			interface_ip.num_wr_ports    =
         // coredynp.decodeW;
@@ -6382,7 +6383,9 @@ void Core::displayEnergy(uint32_t indent, int plevel, bool is_tdp) {
     // cout
     // << indent_str_next << "Peak Dynamic = " <<
     // undiffCore->power.readOp.dynamic*clockRate << " W" << endl;
-    ////				cout << indent_str_next << "Subthreshold Leakage =
+    ////				cout << indent_str_next << "Subthreshold
+    ///Leakage
+    ///=
     ///"
     ///<< undiffCore->power.readOp.leakage <<" W" << endl;
     //				cout << indent_str_next << "Subthreshold Leakage
@@ -6391,10 +6394,14 @@ void Core::displayEnergy(uint32_t indent, int plevel, bool is_tdp) {
     //								<<
     //(long_channel?
     // undiffCore->power.readOp.longer_channel_leakage:undiffCore->power.readOp.leakage)
-    //<< " W" << endl; 				cout << indent_str_next << "Gate Leakage =
+    //<< " W" << endl; 				cout << indent_str_next << "Gate
+    //Leakage
+    //=
     //"
     //<< undiffCore->power.readOp.gate_leakage << " W" << endl;
-    //				//		cout << indent_str_next << "Runtime Dynamic =
+    //				//		cout << indent_str_next << "Runtime
+    //Dynamic
+    //=
     //"
     //<< undiffCore->rt_power.readOp.dynamic/executionTime << " W" << endl;
     // cout
@@ -6411,11 +6418,12 @@ void Core::displayEnergy(uint32_t indent, int plevel, bool is_tdp) {
          << endl;
 
   } else {
-    //		cout << indent_str_next << "Instruction Fetch Unit    Peak Dynamic
+    //		cout << indent_str_next << "Instruction Fetch Unit    Peak
+    // Dynamic
     //=
     //"
     //<< ifu->rt_power.readOp.dynamic*clockRate << " W" << endl;
-    //cout
+    // cout
     //<< indent_str_next << "Instruction Fetch Unit    Subthreshold Leakage = "
     // << ifu->rt_power.readOp.leakage <<" W" << endl; 		cout <<
     // indent_str_next << "Instruction Fetch Unit    Gate Leakage = " <<
@@ -6430,7 +6438,7 @@ void Core::displayEnergy(uint32_t indent, int plevel, bool is_tdp) {
     // << "Load Store Unit   Gate Leakage = " <<
     // lsu->rt_power.readOp.gate_leakage
     //<< " W" << endl; 		cout << indent_str_next << "Memory Management
-    //Unit Peak Dynamic = " << mmu->rt_power.readOp.dynamic*clockRate  << " W"
+    // Unit Peak Dynamic = " << mmu->rt_power.readOp.dynamic*clockRate  << " W"
     // <<
     // endl; 		cout << indent_str_next << "Memory Management Unit
     // Subthreshold Leakage = " << mmu->rt_power.readOp.leakage  << " W" <<
diff --git a/src/gpuwattch/noc.cc b/src/gpuwattch/noc.cc
index 9453ccb..b7ccdb3 100644
--- a/src/gpuwattch/noc.cc
+++ b/src/gpuwattch/noc.cc
@@ -353,11 +353,12 @@ void NoC::displayEnergy(uint32_t indent, int plevel, bool is_tdp) {
       cout << endl;
     }
   } else {
-    //		cout << indent_str_next << "Instruction Fetch Unit    Peak Dynamic
+    //		cout << indent_str_next << "Instruction Fetch Unit    Peak
+    // Dynamic
     //=
     //"
     //<< ifu->rt_power.readOp.dynamic*clockRate << " W" << endl;
-    //cout
+    // cout
     //<< indent_str_next << "Instruction Fetch Unit    Subthreshold Leakage = "
     // << ifu->rt_power.readOp.leakage <<" W" << endl; 		cout <<
     // indent_str_next << "Instruction Fetch Unit    Gate Leakage = " <<
@@ -372,7 +373,7 @@ void NoC::displayEnergy(uint32_t indent, int plevel, bool is_tdp) {
     // << "Load Store Unit   Gate Leakage = " <<
     // lsu->rt_power.readOp.gate_leakage
     //<< " W" << endl; 		cout << indent_str_next << "Memory Management
-    //Unit Peak Dynamic = " << mmu->rt_power.readOp.dynamic*clockRate  << " W"
+    // Unit Peak Dynamic = " << mmu->rt_power.readOp.dynamic*clockRate  << " W"
     // <<
     // endl; 		cout << indent_str_next << "Memory Management Unit
     // Subthreshold Leakage = " << mmu->rt_power.readOp.leakage  << " W" <<
diff --git a/src/gpuwattch/technology_xeon_core.cc b/src/gpuwattch/technology_xeon_core.cc
index 86bbd84..6f95cc2 100644
--- a/src/gpuwattch/technology_xeon_core.cc
+++ b/src/gpuwattch/technology_xeon_core.cc
@@ -1597,8 +1597,8 @@ void init_tech_params(double technology, bool is_tag) {
       //    / Vs 	Vdsat[1] = 6.64e-2; //V/micron 	c_g_ideal[1]
       //    = 3.22e-16;//F/micron 	c_fringe[1] = 0.008e-15; c_junc[1]
       //    =
-      //    0;//F/micron2 	I_on_n[1] = 727.6e-6;//A/micron 	I_on_p[1]
-      //    = I_on_n[1] / 2; 	nmos_effective_resistance_multiplier = 1.99;
+      //    0;//F/micron2 	I_on_n[1] = 727.6e-6;//A/micron I_on_p[1] =
+      //    I_on_n[1] / 2; 	nmos_effective_resistance_multiplier = 1.99;
       //    	n_to_p_eff_curr_drv_ratio[1] = 2;
       //    	gmp_to_gmn_multiplier[1] = 0.99;
       //    	Rnchannelon[1] = nmos_effective_resistance_multiplier * vdd[1] /