update the adaptive cache behaviour and make L1 fully assoc in Volta

9 files changed, 59 insertions, 30 deletions

diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
index f807e11..c0d22ee 100644
--- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
@@ -91,7 +91,7 @@
 # Volta unified cache has four banks
 -l1_banks 4
 #-mem_unit_ports 4
--gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1  S:1:128:256,L:L:s:N:L,A:256:8,16:0,32
 -gpgpu_shmem_size 98304
 -gpgpu_shmem_sizeDefault 98304
 -gpgpu_shmem_per_block 65536
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index 888ce71..0339b0d 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -91,7 +91,7 @@
 # Volta unified cache has four banks
 -l1_banks 4
 #-mem_unit_ports 4
--gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_cache:dl1  S:1:128:256,L:L:s:N:L,A:256:8,16:0,32
 -gpgpu_shmem_size 98304
 -gpgpu_shmem_sizeDefault 98304
 -gpgpu_shmem_per_block 65536
diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index 023f51b..35a3984 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -710,7 +710,7 @@ kernel_info_t::kernel_info_t( dim3 gridDim, dim3 blockDim, class function_info *
     //Jin: launch latency management
     m_launch_latency = g_kernel_launch_latency;
 
-    volta_cache_config_set=false;
+    cache_config_set=false;
 }
 
 /*A snapshot of the texture mappings needs to be stored in the kernel's info as 
@@ -735,7 +735,7 @@ kernel_info_t::kernel_info_t( dim3 gridDim, dim3 blockDim, class function_info *
     //Jin: launch latency management
     m_launch_latency = g_kernel_launch_latency;
 
-    volta_cache_config_set=false;
+    cache_config_set=false;
     m_NameToCudaArray = nameToCudaArray;
     m_NameToTextureInfo = nameToTextureInfo;
 }
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 27a1ba6..231b6a2 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -65,6 +65,11 @@ enum FuncCache
   FuncCachePreferL1 = 2
 };
 
+enum AdaptiveCache
+{
+  FIXED = 0,
+  VOLTA = 1
+};
 
 #ifdef __cplusplus
 
@@ -345,7 +350,7 @@ public:
    unsigned long long end_cycle;
    unsigned m_launch_latency;
 
-   mutable bool volta_cache_config_set;
+   mutable bool cache_config_set;
 };
 
 struct core_config {
@@ -388,7 +393,7 @@ struct core_config {
 	unsigned gpgpu_max_insn_issue_per_warp;
 	bool gmem_skip_L1D; // on = global memory access always skip the L1 cache
 
-	bool adaptive_volta_cache_config;
+	unsigned adaptive_cache_config;
 };
 
 // bounded stack that implements simt reconvergence using pdom mechanism from MICRO'07 paper
diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc
index b0db034..3262456 100644
--- a/src/gpgpu-sim/addrdec.cc
+++ b/src/gpgpu-sim/addrdec.cc
@@ -124,8 +124,8 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, addrdec_
 			* Rau, B. R et al.
 			* ISCA 1991
 			*
-			* equations are adopted from:
-			* "Sacat: streaming-aware conflict-avoiding thrashing-resistant gpgpu cache management scheme."
+			* equations are corresponding to IPOLY(37) and are adopted from:
+			* "SACAT: streaming-aware conflict-avoiding thrashing-resistant gpgpu cache management scheme."
 			* Khairy et al.
 			* IEEE TPDS 2017.
 			*/
diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index db9701d..8d00ea9 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -65,8 +65,13 @@ const char * cache_fail_status_str(enum cache_reservation_fail_reason status)
 
 unsigned l1d_cache_config::set_bank(new_addr_type addr) const{
 
-	if(m_cache_type == SECTOR)
+	//For sector cache, we select one sector per bank (sector interleaving)
+	//This is what was found in Volta (one sector per bank, sector interleaving)
+	//otherwise, line interleaving
+	if(m_cache_type == SECTOR) {
+		//assert(l1_banks == SECTOR_CHUNCK_SIZE);
 		return (addr >> m_sector_sz_log2) & (l1_banks-1);
+	}
 	else
 		return (addr >> m_line_sz_log2) & (l1_banks-1);
 }
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h
index 90adbb5..dd22886 100644
--- a/src/gpgpu-sim/gpu-cache.h
+++ b/src/gpgpu-sim/gpu-cache.h
@@ -656,6 +656,11 @@ public:
         assert( m_valid );
         return MAX_DEFAULT_CACHE_SIZE_MULTIBLIER * m_nset * original_m_assoc;
     }
+    unsigned get_max_assoc() const
+	{
+		assert( m_valid );
+		return MAX_DEFAULT_CACHE_SIZE_MULTIBLIER * original_m_assoc;
+	}
     void print( FILE *fp ) const
     {
         fprintf( fp, "Size = %d B (%d Set x %d-way x %d byte line)\n", 
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc
index 4f071c7..ed94865 100644
--- a/src/gpgpu-sim/gpu-sim.cc
+++ b/src/gpgpu-sim/gpu-sim.cc
@@ -323,7 +323,7 @@ void shader_core_config::reg_options(class OptionParser * opp)
     option_parser_register(opp, "-gpgpu_shmem_size", OPT_UINT32, &gpgpu_shmem_size,
                  "Size of shared memory per shader core (default 16kB)",
                  "16384");
-    option_parser_register(opp, "-adaptive_cache_config", OPT_BOOL, &adaptive_volta_cache_config,
+    option_parser_register(opp, "-adaptive_cache_config", OPT_UINT32, &adaptive_cache_config,
                  "adaptive_cache_config",
                  "0");
     option_parser_register(opp, "-gpgpu_shmem_sizeDefault", OPT_UINT32, &gpgpu_shmem_sizeDefault,
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc
index ffd3035..ff2bf3f 100644
--- a/src/gpgpu-sim/shader.cc
+++ b/src/gpgpu-sim/shader.cc
@@ -2980,33 +2980,47 @@ unsigned int shader_core_config::max_cta( const kernel_info_t &k ) const
        abort();
     }
 
-    if(adaptive_volta_cache_config && !k.volta_cache_config_set) {
-    	//For Volta, we assign the remaining shared memory to L1 cache
-    	//For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
+    if(adaptive_cache_config && !k.cache_config_set) {
+    	//For more info about adaptive cache, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
     	unsigned total_shmed = kernel_info->smem * result;
     	assert(total_shmed >=0 && total_shmed <= gpgpu_shmem_size);
-    	assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared
-    	assert(m_L1D_config.get_nset() == 4);  //Volta L1 has four sets
+    	//assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared
+    	//assert(m_L1D_config.get_nset() == 4);  //Volta L1 has four sets
     	if(total_shmed < gpgpu_shmem_size){
-    		if(total_shmed == 0)
-    			m_L1D_config.set_assoc(256);  //L1 is 128KB ans shd=0
-    		else if(total_shmed > 0 && total_shmed <= 8192)
-    			m_L1D_config.set_assoc(240);  //L1 is 120KB ans shd=8KB
-    		else if(total_shmed > 8192 && total_shmed <= 16384)
-    		    m_L1D_config.set_assoc(224);  //L1 is 112KB ans shd=16KB
-    		else if(total_shmed > 16384 && total_shmed <= 32768)
-    		    m_L1D_config.set_assoc(192);  //L1 is 96KB ans shd=32KB
-    		else if(total_shmed > 32768 && total_shmed <= 65536)
-    		    m_L1D_config.set_assoc(128);	//L1 is 64KB ans shd=64KB
-    		else if(total_shmed > 65536 && total_shmed <= gpgpu_shmem_size)
-    		     m_L1D_config.set_assoc(64); //L1 is 32KB and shd=96KB
-    		else
+    		switch (adaptive_cache_config) {
+    		case FIXED:
+    			break;
+    		case VOLTA: {
+    			//For Volta, we assign the remaining shared memory to L1 cache
+    			//For more info about adaptive cache, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x
+    			assert(gpgpu_shmem_size == 98304); //Volta has 96 KB shared
+
+    			//To Do: make it flexible and not tuned to 9KB share memory
+    			unsigned max_assoc = m_L1D_config.get_max_assoc();
+    			if(total_shmed == 0)
+    				m_L1D_config.set_assoc(max_assoc);  //L1 is 128KB and shd=0
+    			else if(total_shmed > 0 && total_shmed <= 8192)
+    				m_L1D_config.set_assoc(0.9375 * max_assoc);  //L1 is 120KB and shd=8KB
+    			else if(total_shmed > 8192 && total_shmed <= 16384)
+    				m_L1D_config.set_assoc(0.875 * max_assoc);  //L1 is 112KB and shd=16KB
+    			else if(total_shmed > 16384 && total_shmed <= 32768)
+    				m_L1D_config.set_assoc(0.75 * max_assoc);  //L1 is 96KB and shd=32KB
+    			else if(total_shmed > 32768 && total_shmed <= 65536)
+    				m_L1D_config.set_assoc(0.5 * max_assoc);	//L1 is 64KB and shd=64KB
+    			else if(total_shmed > 65536 && total_shmed <= gpgpu_shmem_size)
+    				m_L1D_config.set_assoc(0.25 * max_assoc); //L1 is 32KB and shd=96KB
+    			else
+    				assert(0);
+    			break;
+    		}
+    		default:
     			assert(0);
+    		}
 
-    		 printf ("GPGPU-Sim: Reconfigure L1 cache in Volta Archi to %uKB\n", m_L1D_config.get_total_size_inKB());
+			printf ("GPGPU-Sim: Reconfigure L1 cache to %uKB\n", m_L1D_config.get_total_size_inKB());
     	}
 
-    	k.volta_cache_config_set = true;
+    	k.cache_config_set = true;
     }
 
     return result;