diff options
| author | Mahmoud <[email protected]> | 2019-11-15 20:03:18 -0500 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2019-11-15 20:03:18 -0500 |
| commit | d3316efe70f6007d15f81f828bb5fc82bc5c86d4 (patch) | |
| tree | 0493009e6c4a63dbd2219f189c5914e39fba9a11 | |
| parent | a760eb1c93dd272373089752a821fc8f3eaa9ed3 (diff) | |
invalidate l1 cache at membar
| -rw-r--r-- | src/gpgpu-sim/shader.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/gpgpu-sim/shader.cc b/src/gpgpu-sim/shader.cc index 926453a..19f8e72 100644 --- a/src/gpgpu-sim/shader.cc +++ b/src/gpgpu-sim/shader.cc @@ -3470,6 +3470,14 @@ bool shader_core_ctx::warp_waiting_at_mem_barrier( unsigned warp_id ) return false; if( !m_scoreboard->pendingWrites(warp_id) ) { m_warp[warp_id].clear_membar(); + if (m_gpu->get_config().gpgpu_flush_l1_cache) { + //invalidate L1 cache + //Based on Nvidia Doc, at MEM barrier, we have to + //(1) wait for all pending writes till they are acked + //(2) invalidate L1 cache to ensure coherence and avoid reading stall data + cache_invalidate(); + //TO DO: you need to stall the SM for 5k cycles. + } return false; } return true; |
