fix dram sampling interval scaling

fix dram clock energy scaling

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 17124]

8 files changed, 114 insertions, 58 deletions

diff --git a/CHANGES b/CHANGES
index d22401b..fe73cbc 100644
--- a/CHANGES
+++ b/CHANGES
@@ -87,6 +87,11 @@ Version 3.2.1+edits (development branch) versus 3.2.1
       write-allocation requests from L1 cache are not consumed by the L2 cache. 
     - Fixed a bug that caused allocated local and stack memory to be not correctly
       aligned.
+    - Fix for Bug 67 - updated the DRAM operaion coeff so that it adapts to different
+	  calculation interval. Moved the DRAM related coeffs in XML configuration. Both  
+	  gpuwattch_gtx480.xml and gpuwattch_quadrofx5600.xml are added with GDDR5/GDDR3
+	  coeffs.
+
 
 Version 3.2.1 versus 3.2.0
 - Added kernel name and launch uids to performance statistics log.
diff --git a/configs/GTX480/gpuwattch_gtx480.xml b/configs/GTX480/gpuwattch_gtx480.xml
index 8154c39..304e0fd 100755
--- a/configs/GTX480/gpuwattch_gtx480.xml
+++ b/configs/GTX480/gpuwattch_gtx480.xml
@@ -474,6 +474,16 @@
 			<param name="databus_width" value="32"/>
 			<param name="addressbus_width" value="32"/>
 			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="3.8475e-8f"/>
+			<param name="dram_rd_coeff" value="7.74707143e-8f"/>
+			<param name="dram_wr_coeff" value="3.54664286e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
 
 			<!-- McPAT will add the control bus width to the addressbus width automatically -->
 			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
diff --git a/configs/QuadroFX5600/gpuwattch_quadrofx5600.xml b/configs/QuadroFX5600/gpuwattch_quadrofx5600.xml
index 63a5551..2c5a6fc 100644
--- a/configs/QuadroFX5600/gpuwattch_quadrofx5600.xml
+++ b/configs/QuadroFX5600/gpuwattch_quadrofx5600.xml
@@ -474,6 +474,16 @@
 			<param name="databus_width" value="32"/>
 			<param name="addressbus_width" value="32"/>
 			<param name="PRT_entries" value="32"/>
+			<!-- # of empirical DRAM model parameter -->
+			<param name="dram_cmd_coeff" value="0"/>
+			<param name="dram_act_coeff" value="0"/>
+			<param name="dram_nop_coeff" value="0"/>
+			<param name="dram_activity_coeff" value="0"/>
+			<param name="dram_pre_coeff" value="1.53846154e-8f"/>
+			<param name="dram_rd_coeff" value="3.07692308e-8f"/>
+			<param name="dram_wr_coeff" value="1.30769231e-8f"/>
+			<param name="dram_req_coeff" value="0"/>
+			<param name="dram_const_coeff" value="0"/>
 
 			<!-- McPAT will add the control bus width to the addressbus width automatically -->
 			<stat name="memory_accesses" value="memory_accesses_match_mcpat"/>
diff --git a/src/gpuwattch/XML_Parse.cc b/src/gpuwattch/XML_Parse.cc
index 8e33f3f..39bf2a1 100644
--- a/src/gpuwattch/XML_Parse.cc
+++ b/src/gpuwattch/XML_Parse.cc
@@ -1586,6 +1586,15 @@ void ParseXML::parse(char* filepath)
 				if (strcmp(xNode3.getChildNode("param",k).getAttribute("name"),"type")==0) {sys.mc.type=atoi(xNode3.getChildNode("param",k).getAttribute("value"));continue;}

 				if (strcmp(xNode3.getChildNode("param",k).getAttribute("name"),"withPHY")==0) {sys.mc.withPHY=(bool)atoi(xNode3.getChildNode("param",k).getAttribute("value"));continue;}

 

+        		if (strcmp(xNode3.getChildNode("param",k).getAttribute("name"),"dram_cmd_coeff")==0) {sys.mc.dram_cmd_coeff=atof(xNode3.getChildNode("param",k).getAttribute("value"));continue;}

+        		if (strcmp(xNode3.getChildNode("param",k).getAttribute("name"),"dram_act_coeff")==0) {sys.mc.dram_act_coeff=atof(xNode3.getChildNode("param",k).getAttribute("value"));continue;}

+        		if (strcmp(xNode3.getChildNode("param",k).getAttribute("name"),"dram_nop_coeff")==0) {sys.mc.dram_nop_coeff=atof(xNode3.getChildNode("param",k).getAttribute("value"));continue;}

+        		if (strcmp(xNode3.getChildNode("param",k).getAttribute("name"),"dram_activity_coeff")==0) {sys.mc.dram_activity_coeff=atof(xNode3.getChildNode("param",k).getAttribute("value"));continue;}

+        		if (strcmp(xNode3.getChildNode("param",k).getAttribute("name"),"dram_pre_coeff")==0) {sys.mc.dram_pre_coeff=atof(xNode3.getChildNode("param",k).getAttribute("value"));continue;}

+        		if (strcmp(xNode3.getChildNode("param",k).getAttribute("name"),"dram_rd_coeff")==0) {sys.mc.dram_rd_coeff=atof(xNode3.getChildNode("param",k).getAttribute("value"));continue;}

+        		if (strcmp(xNode3.getChildNode("param",k).getAttribute("name"),"dram_wr_coeff")==0) {sys.mc.dram_wr_coeff=atof(xNode3.getChildNode("param",k).getAttribute("value"));continue;}

+        		if (strcmp(xNode3.getChildNode("param",k).getAttribute("name"),"dram_req_coeff")==0) {sys.mc.dram_req_coeff=atof(xNode3.getChildNode("param",k).getAttribute("value"));continue;}

+        		if (strcmp(xNode3.getChildNode("param",k).getAttribute("name"),"dram_const_coeff")==0) {sys.mc.dram_const_coeff=atof(xNode3.getChildNode("param",k).getAttribute("value"));continue;}

 			}

 			itmp=xNode3.nChildNode("stat");

 			for(k=0; k<itmp; k++)

@@ -2069,6 +2078,7 @@ void ParseXML::initialize() //Initialize all
 	sys.mem.memory_accesses=1;

 	sys.mem.memory_reads=1;

 	sys.mem.memory_writes=1;

+

 	//system_mc

 	sys.mc.mc_clock =1;

 	sys.mc.number_mcs=1;

@@ -2084,6 +2094,7 @@ void ParseXML::initialize() //Initialize all
 	sys.mc.memory_writes=1;

 	sys.mc.LVDS=true;

 	sys.mc.type=1;

+

 	//system_niu

 	sys.niu.clockrate =1;

 	sys.niu.number_units=1;

diff --git a/src/gpuwattch/XML_Parse.h b/src/gpuwattch/XML_Parse.h
index d35ba26..d2f82be 100644
--- a/src/gpuwattch/XML_Parse.h
+++ b/src/gpuwattch/XML_Parse.h
@@ -524,6 +524,7 @@ typedef struct{
 	int output_width_of_DRAM_chip;

 	int page_size_of_DRAM_chip;

 	int burstlength_of_DRAM_chip;

+
 	//stats

 	double memory_accesses;

 	double memory_reads;

@@ -554,6 +555,17 @@ typedef struct{
 	int addressbus_width;

 	int PRT_entries;

 	bool LVDS;

+
+	// emprical DRAM coeff
+	double dram_cmd_coeff;
+	double dram_act_coeff;
+	double dram_nop_coeff;
+	double dram_activity_coeff;
+	double dram_pre_coeff;
+	double dram_rd_coeff;
+	double dram_wr_coeff;
+	double dram_req_coeff;
+	double dram_const_coeff;
 

 	//stats

 	double memory_accesses;

diff --git a/src/gpuwattch/basic_components.h b/src/gpuwattch/basic_components.h
index ee4b725..7e4c962 100644
--- a/src/gpuwattch/basic_components.h
+++ b/src/gpuwattch/basic_components.h
@@ -200,7 +200,7 @@ public:
 	DRAMParam(ParseXML *XML_interface, int ithCache_);
     string name;
     double  clockRate;
-    double executionTim;
+    double executionTime;
     double cmd_coeff;
     double activity_coeff;
     double nop_coeff;
@@ -211,6 +211,49 @@ public:
     double req_coeff;
     double const_coeff;
 
+	int detailed_dram_model; // 1 - to use newly added DRAM model (GDDR5 only), 0 - use empirical model
+	// the following are the current specified by DATA SHEET
+	// unit: mA
+	int idd0;
+	int idd1;
+	int idd2p;
+	int idd2n;
+	int idd3p;
+	int idd3n;
+	int idd4r;
+	int idd4w;
+	int idd5;
+	int idd6;
+	int idd7;
+
+	// the following are the vdd specified by DATA SHEET; NOT the actual VDD
+	double datasheet_vdd;
+	double actual_vdd;
+
+	// the following are the timing parameters specified by DATA SHEET
+	// unit: ns
+	int t_ccd;
+	int t_rrd;
+	int t_rcd;
+	int t_ras;
+	int t_rp;
+	int t_rc;
+	int t_cl;
+	int t_cdlr;
+	int t_wr;
+
+	// the following are the DRAM clocks
+	// unit: MHz
+	int datasheet_operating_clock; // this is specified by DATA SHEET. This is NOT the actual DRAM clock
+	int actual_operating_clock;
+
+	// the following are each DRAM bank's IO info
+	int bank_width; // in bits
+	int dqs_signal_width; // in bits
+	int extra_dq_write_signal_width; //in bits
+	int per_dq_read_power; // in mW
+	int per_dq_write_power; // in mW
+
     ~DRAMParam(){};
 };
 
diff --git a/src/gpuwattch/memoryctrl.cc b/src/gpuwattch/memoryctrl.cc
index b8a8a6c..d145ce1 100644
--- a/src/gpuwattch/memoryctrl.cc
+++ b/src/gpuwattch/memoryctrl.cc
@@ -483,30 +483,18 @@ MCFrontEnd::MCFrontEnd(ParseXML *XML_interface,InputParameter* interface_ip_, co
 void DRAM::computeEnergy(bool is_tdp)
 {
 	if (is_tdp){
-			power.reset();
-
-	}
-	else{
-			rt_power.reset();
-			dramp.executionTim   = XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6);
+		power.reset();
+		return; /// not supporting TDP calculation for DRAM
 	}
+	rt_power.reset();
+	dramp.executionTime   = XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6);
 
 	power_t.reset();
-	power_t.readOp.dynamic+=XML->sys.mc.memory_reads*dramp.rd_coeff*dramp.executionTim;
-	power_t.readOp.dynamic+=XML->sys.mc.memory_writes*dramp.wr_coeff*dramp.executionTim;
-	power_t.readOp.dynamic+=XML->sys.mc.dram_pre*dramp.pre_coeff*dramp.executionTim;
-	if (is_tdp){
-			power.reset();
-
-	}
-	else{
-			//rt_power.reset();
-			rt_power = rt_power + power_t ;
-			//printf("DRAM power: %f total_cycles: %f target_clock_rate: %f\n",rt_power.readOp.dynamic/dramp.executionTim,
-			//	XML->sys.total_cycles,(XML->sys.target_core_clockrate*1e6)	);
-	}
-
+	power_t.readOp.dynamic+=XML->sys.mc.memory_reads*dramp.rd_coeff;
+	power_t.readOp.dynamic+=XML->sys.mc.memory_writes*dramp.wr_coeff;
+	power_t.readOp.dynamic+=XML->sys.mc.dram_pre*dramp.pre_coeff;
 
+	rt_power = rt_power + power_t ;
 }
 
 
@@ -914,43 +902,20 @@ void MemoryController::displayEnergy(uint32_t indent,int plevel,bool is_tdp)
 	}
 
 }
+
 void DRAM::set_dram_param()
 {
-	if (dram_type==GDDR5)
-	{
-	    dramp.clockRate=XML->sys.mc.mc_clock*2*1e6;
-	    dramp.executionTim=XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6);
-	    dramp.cmd_coeff=0;
-	    dramp.act_coeff=0;
-	    dramp.nop_coeff=0;
-	    dramp.activity_coeff=0;
-
-	    dramp.pre_coeff=0.81*0.0665;// 0.0383;//0.0395;//0.0401637266720557;//0.0092780790143343;//0.005;//*dramp.executionTim;
-	    dramp.rd_coeff= 0.81*0.1339;// 0.0653;//0.064;//0.0624228500824509;//0.0565534489065191;//0.0446;//*dramp.executionTim;
-	    dramp.wr_coeff=  0.81*0.0613;//0.0067;//0.006;//0.0251181528358946;//0.015;//0.0079;//*dramp.executionTim;
-	    dramp.req_coeff=0;
-	    dramp.const_coeff=0;
-
-	}else if (dram_type==GDDR3)
-	{
-	    dramp.clockRate=XML->sys.mc.mc_clock*2*1e6;
-	    dramp.executionTim=XML->sys.total_cycles/(XML->sys.target_core_clockrate*1e6);
-	    dramp.cmd_coeff=0;
-	    dramp.act_coeff=0;
-	    dramp.nop_coeff=0;
-	    dramp.activity_coeff=0;
-
-	    dramp.pre_coeff=0.020;//0.0665;// 0.0383;//0.0395;//0.0401637266720557;//0.0092780790143343;//0.005;//*dramp.executionTim;
-	    dramp.rd_coeff= 0.040;//0.1339;// 0.0653;//0.064;//0.0624228500824509;//0.0565534489065191;//0.0446;//*dramp.executionTim;
-	    dramp.wr_coeff=  0.017;//0.0213;//0.0067;//0.006;//0.0251181528358946;//0.015;//0.0079;//*dramp.executionTim;
-	    dramp.req_coeff=0;
-	    dramp.const_coeff=0;
-	}else
-	{
-		cout<<"Unknown DRAM type" <<endl;
-		exit(0);
-	}
+	dramp.cmd_coeff 		= XML->sys.mc.dram_rd_coeff;
+	dramp.act_coeff 		= XML->sys.mc.dram_act_coeff;
+	dramp.nop_coeff			= XML->sys.mc.dram_nop_coeff;
+	dramp.activity_coeff 	= XML->sys.mc.dram_activity_coeff;
+	dramp.pre_coeff			= XML->sys.mc.dram_pre_coeff;
+	dramp.rd_coeff			= XML->sys.mc.dram_rd_coeff;
+	dramp.wr_coeff			= XML->sys.mc.dram_wr_coeff;
+	dramp.req_coeff			= XML->sys.mc.dram_req_coeff;
+	dramp.const_coeff		= XML->sys.mc.dram_const_coeff;
 }
+
 void MemoryController::set_mc_param()
 {
 
diff --git a/src/gpuwattch/processor.h b/src/gpuwattch/processor.h
index 46d954e..7202460 100644
--- a/src/gpuwattch/processor.h
+++ b/src/gpuwattch/processor.h
@@ -195,7 +195,7 @@ class Processor : public Component
 		value+=(mc->frontend->mcp.llcBlockSize*8.0/mc->mcp.dataBusWidth)*
 		  (mc->frontend->readBuffer->local_result.power.writeOp.dynamic);
 
-		value+=mc->dram->dramp.rd_coeff*cores[0]->executionTime;
+		value+=mc->dram->dramp.rd_coeff;
 		/*
 			value+=mc->frontend->PRT->local_result.power.readOp.dynamic;
 			value+=mc->frontend->threadMasks->local_result.power.readOp.dynamic;
@@ -239,7 +239,7 @@ class Processor : public Component
 		value+=(mc->frontend->mcp.llcBlockSize*8.0/mc->frontend->mcp.dataBusWidth)*
 		  (mc->frontend->writeBuffer->local_result.power.writeOp.dynamic);
 
-		value+=mc->dram->dramp.wr_coeff*cores[0]->executionTime;
+		value+=mc->dram->dramp.wr_coeff;
 		/*
 			value+=(mc->frontend->PRT->local_result.power.writeOp.dynamic);
 
@@ -273,7 +273,7 @@ class Processor : public Component
 	 double get_coefficient_mem_pre()
 	 {
 		double value=0;
-		value+=mc->dram->dramp.pre_coeff*cores[0]->executionTime;
+		value+=mc->dram->dramp.pre_coeff;
 		//return 0.4*value;
 		return value;